diff options
| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-19 08:59:01 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-25 00:19:50 +0000 |
| commit | 7e96518e63470b21fb001cacfc0a19b5e98167e7 (patch) | |
| tree | 113b2044d6eed51090de45c87bf6eea1f62ddbe3 /src/soc/amd/cezanne | |
| parent | 56823f53dc6de5a804f7c88b9f24847133ddc876 (diff) | |
soc/amd/cezanne/acpi/pci0.asl: Add LPC device
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne')
| -rw-r--r-- | src/soc/amd/cezanne/acpi/pci0.asl | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl index f9c732f9b0..f9956b68c5 100644 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ b/src/soc/amd/cezanne/acpi/pci0.asl @@ -78,4 +78,7 @@ Device(PCI0) { Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ + /* 0:14.3 - LPC */ + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ |