From 7e96518e63470b21fb001cacfc0a19b5e98167e7 Mon Sep 17 00:00:00 2001
From: Raul E Rangel <rrangel@chromium.org>
Date: Fri, 19 Feb 2021 08:59:01 -0700
Subject: soc/amd/cezanne/acpi/pci0.asl: Add LPC device

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/cezanne/acpi/pci0.asl | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/soc/amd/cezanne')

diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
index f9c732f9b0..f9956b68c5 100644
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ b/src/soc/amd/cezanne/acpi/pci0.asl
@@ -78,4 +78,7 @@ Device(PCI0) {
 		Return(CRES) /* note to change the Name buffer */
 	} /* end of Method(_SB.PCI0._CRS) */
 
+	/* 0:14.3 - LPC */
+	#include <soc/amd/common/acpi/lpc.asl>
+
 } /* End PCI0 scope */
-- 
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