soc/amd: commonize PCI root IOAPIC initialization

Make the initialization of the IOAPIC(s) in the PCI root(s) common
across all AMD family 17h+ SoCs. For this the more general
implementation from the Genoa code that supports multiple PC roots is
moved to the common AMD code. All other family 17h+ SoCs are then
adapted to use the common code. For those non-Genoa SoCs, the
initialization of this second IOAPIC is moved from the northbridge
device to the domain device above to match Genoa.

Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized
on Mandolin

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80286
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 6 deletions

diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index 0fb086fc50..72a24199e2 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -42,11 +42,6 @@ struct dptc_input {
 		},								\
 	}
 
-static void root_complex_init(struct device *dev)
-{
-	register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);
-}
-
 static void acipgen_dptci(void)
 {
 	const struct soc_amd_cezanne_config *config = config_of_soc();
@@ -76,7 +71,6 @@ struct device_operations cezanne_root_complex_operations = {
 	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= root_complex_init,
 	.acpi_name		= gnb_acpi_name,
 	.acpi_fill_ssdt		= root_complex_fill_ssdt,
 };