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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-14 01:40:50 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-24 18:15:46 +0000 |
| commit | 8d0a609e6d1bfb48de781e7223f73ff979d0ce2e (patch) | |
| tree | d3f40d275aeff99da11287de34bcc1bb62f7a2d6 /src/soc/amd/cezanne/romstage.c | |
| parent | 45b0714c89db4487074e87ada13b9886c43d9ccd (diff) | |
soc,vendorcode/amd/cezanne: add basic FSP integration
This is a trimmed-down version of the Cezanne FSP integration code, so
for example the UPD definitions are empty, which will be addressed
later. Since coreboot just leaves the UPD values at their default, this
is not a problem during the initial platform bring-up.
Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/romstage.c')
| -rw-r--r-- | src/soc/amd/cezanne/romstage.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 91074b2012..52ff0f8e41 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -1,6 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cpu.h> +#include <fsp/api.h> + +void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) +{ +} asmlinkage void car_stage_entry(void) { |