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authorMario Scheithauer <mario.scheithauer@siemens.com>2022-09-29 15:25:48 +0200
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-10-07 22:03:45 +0000
commitc8c64c12a55a13116f33d00ebbf64e647f161a23 (patch)
tree76210eafe242bae7f1f25a67f0f953a269272374 /src/soc/amd/cezanne/reset.c
parentfb9110b9e4f787ab8327b005fccf44d5961c991b (diff)
soc/intel/ehl: Set Ethernet controller to D0 power state
To be able to change the MAC addresses, it is necessary that the controllers are in D0 power state. As of FSP MR3, Intel has set the controllers to D3 power state at the end of FSP-S TSN GbE initialization. This patch sets the state back to D0 before the programming of the MAC addresses. Test: - Build coreboot with FSP MR4 for mc_ehl2 mainboard - Boot into Linux and check MAC addr via 'ip a' Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/amd/cezanne/reset.c')
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