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| author | Cliff Huang <cliff.huang@intel.corp-partner.google.com> | 2022-04-28 18:06:54 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-09 13:39:38 +0000 |
| commit | 61a442ec01b1a7d9a2d83604956f8355ea391b3e (patch) | |
| tree | fca3920033f33bc512af9772fb2a746e255744e1 /src/soc/amd/cezanne/reset.c | |
| parent | 76ef18d8ffa97844a09268c7459c7fcf0a5f10af (diff) | |
soc/intel/alderlake: Add support for PCIe slot & device detect timeout
1. add timeout for root port detection and pass to FSP.
2. add 'slot implemented' flag and pass to FSP.
3. PcieRpSlotImplemented needs to be set when the root port is set to
hotplug. There is an assertion in FSP checking this.
4. PcieRpSlotImplemented is updated only when it is built-in as it is
default to slot implemented in FSP.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/cezanne/reset.c')
0 files changed, 0 insertions, 0 deletions