summaryrefslogtreecommitdiff
path: root/src/soc/amd/cezanne/fch.c
diff options
context:
space:
mode:
authorjzhao80 <john.zhao@intel.com>2022-01-10 07:54:57 -0800
committerFelix Held <felix-coreboot@felixheld.de>2022-01-12 16:09:47 +0000
commit6c4edff487d365d40fbd6fb0eb3332492a947ada (patch)
tree6febc7ba6aa1a6878343a83f5e270b0dd5d9a771 /src/soc/amd/cezanne/fch.c
parenta421b1a289fd173da609a4d1e2625c44ad1faad4 (diff)
soc/intel/tigerlake: Implement function to map physical port to EC port
Currently coreboot and EC had different logic to interpret TCSS port number which would break retimer update functionality since coreboot would pass wrong port information to EC. This change clones the implementation on Alder Lake which converts the phyiscal port mapping to EC's abstract port mapping. BUG=b:207057940 BRANCH=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/amd/cezanne/fch.c')
0 files changed, 0 insertions, 0 deletions