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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-22 17:41:38 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-30 19:46:17 +0000 |
| commit | fd2982ec8a61894d466efc47a9d724a93af6ddc6 (patch) | |
| tree | f8216b351fb0109a9c807bfa1fda8edfed7aa95e /src/soc/amd/cezanne/chipset.cb | |
| parent | ce5813fdc5d527803ab560cec5e798a04b210d3e (diff) | |
soc/amd/cezanne/fch: implement and use fch_clk_output_48Mhz
Make sure that the 48MHz clock output that is typically used as a clock
source for an I2S audio codec or a Super I/O chip.
TEST=On Guybrush before and after this patch the final state of
MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/chipset.cb')
0 files changed, 0 insertions, 0 deletions