diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 20:50:08 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-09 00:10:00 +0000 |
| commit | ed6c99990439b51a7b3b03dd5d4d122b69ddbc58 (patch) | |
| tree | 6b2a6db96a4e35c4dad4613859934867ebd32d9f /src/soc/amd/cezanne/chipset.cb | |
| parent | 8880baf6bc55a16485f523113e72f119cc9da8c5 (diff) | |
soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree
Instead of adding the new PCI IDs of the XHCI controllers in every new
chip generation to the pci_xhci driver, bind the driver to the internal
PCI devices of the XHCI controllers via the device ops statement in the
chipset devicetree. The PCI device function of the XHCI2 controller in
Mendocino can be either a dummy device or the XHCI controller, so the
device ops are attached to that device in the mainboard devicetree
instead. The Glinda code is right now just a copy of the Mendocino code,
so it'll change in the future, but for consistency the equivalent
changes to those in Mendocino are applied there too.
Since the device ops are now attached to the devices via the static
devicetree entry, also remove both the xhci_pci_driver struct and the
amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c.
TEST=SSDT entries for the XHCI controllers are still generated on
Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/cezanne/chipset.cb')
| -rw-r--r-- | src/soc/amd/cezanne/chipset.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index c7793905ae..0762ea1d26 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -28,6 +28,7 @@ chip soc/amd/cezanne device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -53,6 +54,7 @@ chip soc/amd/cezanne end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off |