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authorFelix Held <felix-coreboot@felixheld.de>2024-03-05 18:29:01 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-05-15 15:01:05 +0000
commitd7158c81495e6fd7ae766a08669184798008308f (patch)
tree94ed85a88cc4ec9d5a491726dca8e32383015f3a /src/soc/amd/cezanne/chip.h
parent7728ed3ea2139908ab8e9a0c43b6ccdf7b1020d6 (diff)
mb/amd/birman/devicetree_phoenix_opensil: add stub MPIO chips
Add the stub MPIO chips that contain the PCIe engine configuration for the external PCIe interfaces to the devicetree. Birman's port_descriptors_phoenix.c was used as a reference. The static configuration in the devicetree assumes that the default WLAN0_WWAN0 is selected; for the other cases we'll still need to fix up things accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still need to be handled in a follow-up patch. Since openSIL currently doesn't use the info from the gpio_group struct element, but deasserts both PCIe reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip configuration in the devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/81101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd/cezanne/chip.h')
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