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authorFelix Held <felix-coreboot@felixheld.de>2021-02-05 21:46:53 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-02-07 17:48:48 +0000
commit5a7e4a59821905350c1cdfc3ddbf571c041d800e (patch)
treedea8e677120eacc9fa89d5fc44b902b4f61ff579 /src/soc/amd/cezanne/chip.c
parentb726e091575aa979e3a57565692bfb8dc53b0915 (diff)
soc/amd/cezanne/chip: add PCI bus scanning
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I76b0eb4470ac4a48e1caeaf507b5e6c45bb88119 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/chip.c')
-rw-r--r--src/soc/amd/cezanne/chip.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index 4a39024b1b..f6cac149f4 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -7,8 +7,22 @@
#include <types.h>
#include "chip.h"
+static struct device_operations pci_domain_ops = {
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = pci_domain_scan_bus,
+};
+
static void enable_dev(struct device *dev)
{
+ /* Set the operations if it is a special bus type */
+ switch (dev->path.type) {
+ case DEVICE_PATH_DOMAIN:
+ dev->ops = &pci_domain_ops;
+ break;
+ default:
+ break;
+ }
}
static void soc_init(void *chip_info)