diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-17 02:52:03 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-18 14:06:30 +0000 |
| commit | 5c56b16533313e5d7cce213357fc22a52e14d899 (patch) | |
| tree | db48a087aa2eecdf0f915362d79feac15b8f6b2c /src/soc/amd/cezanne/agesa_acpi.c | |
| parent | 4235fb6015b7f1ac78b21209cf2ff32b8eb27458 (diff) | |
soc/amd/*/agesa_acpi: add TODO for adding CRAT table
The Picasso SoC code generates a CRAT ACPI table which is not done for
Cezanne and newer. A significant part of the Picasso CRAT generation
code can likely be moved to the common AMD SoC code and then used in all
SoCs, but this still needs to be checked.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f1ebe74f0376c60396dbd80e64676d1374ed811
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72027
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/agesa_acpi.c')
| -rw-r--r-- | src/soc/amd/cezanne/agesa_acpi.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/agesa_acpi.c b/src/soc/amd/cezanne/agesa_acpi.c index ce4753b092..fdfe3eb3d7 100644 --- a/src/soc/amd/cezanne/agesa_acpi.c +++ b/src/soc/amd/cezanne/agesa_acpi.c @@ -12,6 +12,8 @@ uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current { acpi_ivrs_t *ivrs; + /* TODO: look into adding CRAT */ + /* add ALIB SSDT from HOB */ current = acpi_align_current(current); current = add_agesa_fsp_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); |