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| author | Raul E Rangel <rrangel@chromium.org> | 2021-02-24 16:59:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-01 08:27:57 +0000 |
| commit | 97b8b1760075d3bdfedc3189df96f06162eb0c9d (patch) | |
| tree | 6b10cef4737de12b4c469c51ff124a1d2433ea62 /src/soc/amd/cezanne/Makefile.inc | |
| parent | 2c30a83d9be67f397598baa1e0eb2f6f188b12a4 (diff) | |
soc/amd/cezanne: Add PSP whitelist debug unlock support
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index d631c63495..35e700977e 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -85,6 +85,11 @@ else PSP_SOFTFUSE_BITS += 29 endif +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + # # BIOS Directory Table items - proper ordering is managed by amdfwtool # @@ -134,6 +139,8 @@ OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), -- OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) + # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) @@ -149,6 +156,7 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ --load-s0i3 \ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ + $(OPT_WHITELIST_FILE) \ $(OPT_EFS_SPI_READ_MODE) \ $(OPT_EFS_SPI_SPEED) \ $(OPT_EFS_SPI_MICRON_FLAG) \ |