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authorFelix Held <felix-coreboot@felixheld.de>2020-12-09 02:01:16 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-11 17:44:42 +0000
commit44f41537af4022ce8d8c4fadb6b690b3ec6f8c61 (patch)
treed28b4299b86f996f768f723c2a844a0146c3c606 /src/soc/amd/cezanne/Makefile.inc
parente04a18fc25cfb28690cd7dbd3302a63436b1ccd2 (diff)
soc/amd/cezanne: add 0xcf9 reset
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/amd/cezanne/Makefile.inc')
-rw-r--r--src/soc/amd/cezanne/Makefile.inc5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index e7d0aea560..353bdbe891 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -7,10 +7,15 @@ all-y += config.c
bootblock-y += bootblock.c
bootblock-y += early_fch.c
+bootblock-y += reset.c
+verstage_x86-y += reset.c
+
+romstage-y += reset.c
romstage-y += romstage.c
ramstage-y += chip.c
+ramstage-y += reset.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include