From 44f41537af4022ce8d8c4fadb6b690b3ec6f8c61 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 9 Dec 2020 02:01:16 +0100 Subject: soc/amd/cezanne: add 0xcf9 reset Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson Reviewed-by: Mathew King Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/Makefile.inc | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/soc/amd/cezanne/Makefile.inc') diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index e7d0aea560..353bdbe891 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -7,10 +7,15 @@ all-y += config.c bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += reset.c +verstage_x86-y += reset.c + +romstage-y += reset.c romstage-y += romstage.c ramstage-y += chip.c +ramstage-y += reset.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include -- cgit v1.2.3