diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-05-31 16:08:42 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-07 00:18:28 +0000 |
| commit | 9adc33d0d080f11db33ecc7fb25be93c8507c36f (patch) | |
| tree | b48da7b00ab6dd9ca3b0e171ba1c4af699b6dcc8 /src/soc/amd/cezanne/Kconfig | |
| parent | e4b65cc945bb5256fdb65041b9f4d20c05155cd8 (diff) | |
soc/amd/cezanne/chip: use common data fabric domain resource code
Use the new common AMD code that gets the usable non-fixed MMIO windows
from the data fabric MMIO decode registers and generate the PCI0 _CRS
ACPI code based on those regions. For a more detailed description see
the corresponding patch that changes the Picasso code to use this new
code. In contrast to the Picasso code, this change will drop the
unneeded _STA method inside the PCI0 scope which wasn't present in
Picasso's ACPI code before it got replaced by the SSDT that gets
generated by amd_pci_domain_fill_ssdt.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b14ee0682ae1f2212ab43977c076687706434ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75557
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/amd/cezanne/Kconfig')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 2975dda48e..e96169b9cc 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -41,6 +41,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI |