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authorAngel Pons <th3fanbus@gmail.com>2020-02-17 14:04:28 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 13:04:39 +0000
commit31b7ee42016f7b54c24f30c271b4b93df16bfa10 (patch)
treeae4d33670204b4e09e228ff3d28385e76da7210d /src/security/tpm
parent95de2317c6c6379e43d3b3c27d34eb66198dbe0a (diff)
treewide: Replace uses of "Nehalem"
The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/security/tpm')
-rw-r--r--src/security/tpm/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig
index 95c0bb9b7d..fbe1735707 100644
--- a/src/security/tpm/Kconfig
+++ b/src/security/tpm/Kconfig
@@ -99,7 +99,7 @@ config TPM_STARTUP_IGNORE_POSTINIT
Select this to ignore POSTINIT INVALID return codes on TPM
startup. This is useful on platforms where a previous stage
issued a TPM startup. Examples of use cases are Intel TXT
- or VBOOT on the Intel Nehalem northbridge which issues a
+ or VBOOT on the Intel Arrandale processor, which issues a
CPU-only reset during the romstage.
endmenu # Trusted Platform Module (tpm)