diff options
| author | Keith Short <keithshort@chromium.org> | 2019-02-05 16:15:10 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-13 13:03:33 +0000 |
| commit | e0f340054761086e4c329a2f66bb8f5b6e13d7c9 (patch) | |
| tree | 977ba95155edd474d6d67c4bf61f58ee869c094f /src/security/tpm/tss_errors.h | |
| parent | 91be00ef1be29e6670599aa5e9c297854a928d07 (diff) | |
coreboot: check Cr50 PM mode on normal boot
Under some scenarios the key ladder on the Cr50 can get disabled. If
this state is detected, trigger a reboot of the Cr50 to restore full
TPM functionality.
BUG=b:121463033
BRANCH=none
TEST=Built coreboot on sarien and grunt platforms.
TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends
VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and
then the platform boots normally.
TEST=Performed Cr50 rollback to 0.0.22 which does not support the
VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and
the coreboot log captures the unsupported command.
Tested-by: Keith Short <keithshort@chromium.org>
Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/security/tpm/tss_errors.h')
| -rw-r--r-- | src/security/tpm/tss_errors.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index 316661cd0a..ed6fc3d77c 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -42,5 +42,6 @@ #define TPM_E_NV_DEFINED ((uint32_t)0x0000500b) /* vboot local */ #define TPM_E_INVALID_ARG ((uint32_t)0x0000500c) #define TPM_E_HASH_ERROR ((uint32_t)0x0000500d) +#define TPM_E_NO_SUCH_COMMAND ((uint32_t)0x0000500e) #endif /* TSS_ERRORS_H_ */ |