diff options
| author | Keith Short <keithshort@chromium.org> | 2019-01-11 07:52:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-17 13:01:52 +0000 |
| commit | e371d421137901043ba495f8e4f5063be26b6764 (patch) | |
| tree | bc938bc8baad7084fea948eb9c3dfdd0743d9d05 /src/security/tpm/tss/vendor/cr50 | |
| parent | 49bfdb35f47bdce0b53c553b3b6fb67bcbc8796e (diff) | |
src/security/tpm: query recovery mode from Cr50
On the Sarien/Arcada platforms, the EC is not trusted to provide
the state of the ESC+REFRESH+PWR recovery combination. On these
platforms the Cr50 latches the state of REFRESH+PWR for use as the
recovery mode key combination.
BUG=b:122715254
BRANCH=none
TEST=Verify recovery mode screen shown after pressing REFRESH+PWR
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ie3ce519956f916023c8c52f1d11fa93331f52f3c
Reviewed-on: https://review.coreboot.org/c/30929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/security/tpm/tss/vendor/cr50')
| -rw-r--r-- | src/security/tpm/tss/vendor/cr50/cr50.c | 16 | ||||
| -rw-r--r-- | src/security/tpm/tss/vendor/cr50/cr50.h | 9 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/security/tpm/tss/vendor/cr50/cr50.c b/src/security/tpm/tss/vendor/cr50/cr50.c index 90f796379c..450ad97fe5 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.c +++ b/src/security/tpm/tss/vendor/cr50/cr50.c @@ -52,3 +52,19 @@ uint32_t tlcl_cr50_enable_update(uint16_t timeout_ms, *num_restored_headers = response->vcr.num_restored_headers; return TPM_SUCCESS; } + +uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state) +{ + struct tpm2_response *response; + uint16_t sub_command = TPM2_CR50_SUB_CMD_GET_REC_BTN; + + printk(BIOS_INFO, "Checking cr50 for recovery request\n"); + + response = tpm_process_command(TPM2_CR50_VENDOR_COMMAND, &sub_command); + + if (!response || response->hdr.tpm_code) + return TPM_E_INTERNAL_INCONSISTENCY; + + *recovery_button_state = response->vcr.recovery_button_state; + return TPM_SUCCESS; +} diff --git a/src/security/tpm/tss/vendor/cr50/cr50.h b/src/security/tpm/tss/vendor/cr50/cr50.h index 9bf3bd5f79..a1ab539c07 100644 --- a/src/security/tpm/tss/vendor/cr50/cr50.h +++ b/src/security/tpm/tss/vendor/cr50/cr50.h @@ -25,6 +25,7 @@ #define TPM2_CR50_VENDOR_COMMAND ((TPM_CC)(TPM_CC_VENDOR_BIT_MASK | 0)) #define TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS (21) #define TPM2_CR50_SUB_CMD_TURN_UPDATE_ON (24) +#define TPM2_CR50_SUB_CMD_GET_REC_BTN (29) /** * CR50 specific tpm command to enable nvmem commits before internal timeout @@ -44,4 +45,12 @@ uint32_t tlcl_cr50_enable_nvcommits(void); uint32_t tlcl_cr50_enable_update(uint16_t timeout_ms, uint8_t *num_restored_headers); +/** + * CR50 specific tpm command to get the latched state of the recovery button. + * + * Return value indicates success or failure of accessing the TPM; in case of + * success the recovery button state is saved in recovery_button_state. + */ +uint32_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state); + #endif /* CR50_TSS_STRUCTURES_H_ */ |