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authorWerner Zeh <werner.zeh@siemens.com>2021-11-16 08:02:22 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-11-17 14:27:03 +0000
commit98c7d55eaac8841909ea120aaef9199ae7ee872c (patch)
tree9ec0365e9b86ba6a2f69b950101818c9528c8089 /src/security/intel/txt
parent42b8835beb45c15c46621b6877d337b35df3bffd (diff)
mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI
This board does not have a LPC or eSPI connection to the NC FPGA anymore and therefore IO port 0x80 is not useable for POST codes anymore. Enable the feature of sending the POST codes to the NC FPGA via PCI so that the POST codes are visbile again in coreboot. Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/security/intel/txt')
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