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authorFelix Held <felix-coreboot@felixheld.de>2022-10-18 19:28:50 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-10-20 16:40:45 +0000
commitacd98d87722adbf8cc94c770881cf3105b02786f (patch)
tree00077f4c583d39e312fd8d4f09a1177a5fba09b6 /src/sbom/payload-skiboot.json
parentd2ebe16cb40a2a0dbd941fc48e1fce0a2cf51215 (diff)
soc/amd/stoneyridge/uart: add and use uart_info array
Introduce and use an array of soc_uart_ctrlr_info to align Stoneyridge with the other AMD SoCs in order to allow commonization of the AMD SoC UART code. Since the current Stoneyridge code doesn't provide or use UART MMIO device operations, only the base addresses of the UART controllers from this array are used for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie868cd3e2f77b0f7253c9f6d91dd3bbc3e4b6b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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