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| author | Maximilian Brune <maximilian.brune@9elements.com> | 2024-08-09 13:48:58 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-11-18 01:23:14 +0000 |
| commit | a9e5ab7bb00ec2363abea4e44baf98a8130fbb2e (patch) | |
| tree | 0afebdd288177fc9dcb27f817f84ae4df6eda774 /src/sbom/intel-microcode.json | |
| parent | 02847233f8fcc3b15866ab53f230bdfff3056246 (diff) | |
Documentation/acronyms.md: Add some acronyms
These acronyms have been found while looking at the datasheet of the
JH7110 RISC-V SOC.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I82104b88e7723b73810f20d5f4dffe6ed8a9ab78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83847
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/sbom/intel-microcode.json')
0 files changed, 0 insertions, 0 deletions