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| author | Alper Nebi Yasak <alpernebiyasak@gmail.com> | 2024-04-24 22:24:51 +0300 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-07-11 11:03:31 +0000 |
| commit | 795994e025365c1db81cadf0b8544425de57516f (patch) | |
| tree | 73c1133df229d995e63c9c02aff3873e2bc2aa4b /src/sbom/intel-me.json | |
| parent | 7ac0f5b9693929ce8cc1486a67c9a46e3a0af2d2 (diff) | |
mainboard/qemu-aarch64: Set CONFIG_PCI_IOBASE to 0x3eff0000
Define the PCI I/O base address necessary to use port I/O functions on
the qemu-aarch64 mainboard, so that we can get the VGA display devices
working. The config value is from hw/arm/virt.c [1]:
[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
[1] https://gitlab.com/qemu-project/qemu/-/blob/v8.2.3/hw/arm/virt.c#L164
Change-Id: I85439ba68740d64f789983b37d9c95f849ce4f72
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82059
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/sbom/intel-me.json')
0 files changed, 0 insertions, 0 deletions