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authorKyösti Mälkki <kyosti.malkki@gmail.com>2023-04-09 10:01:58 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2023-04-13 18:48:29 +0000
commitd1534e41e4172b121122b2802d45028b61234279 (patch)
treeb1312eaf4918a1275f638211e8a6d3f4d8cf7946 /src/northbridge
parent8f86fa0da17a7f5ec981fdf09ebb2c6a3c17b2f6 (diff)
AMD binaryPI: Use madt_ioapic_from_hw()
Read IOAPIC ID and number of interrupts from programmed registers. Change-Id: Ic8ba395bc220fdb691118719f7b32dd7400931f4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/pi/00730F01/acpi_tables.c7
-rw-r--r--src/northbridge/amd/pi/00730F01/northbridge.c8
-rw-r--r--src/northbridge/amd/pi/00730F01/state_machine.c2
3 files changed, 6 insertions, 11 deletions
diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c
index bb510cd72c..ef240c12a3 100644
--- a/src/northbridge/amd/pi/00730F01/acpi_tables.c
+++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c
@@ -3,7 +3,6 @@
#include <acpi/acpi.h>
#include <arch/ioapic.h>
#include <northbridge/amd/nb_common.h>
-#include <southbridge/amd/pi/hudson/ioapic.h>
unsigned long acpi_fill_madt(unsigned long current)
{
@@ -11,12 +10,10 @@ unsigned long acpi_fill_madt(unsigned long current)
current = acpi_create_madt_lapics_with_nmis(current);
/* Write SB800 IOAPIC, only one */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, FCH_IOAPIC_ID,
- IO_APIC_ADDR, 0);
+ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR);
/* TODO: Remove the hardcode */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, GNB_IOAPIC_ID,
- IO_APIC2_ADDR, 24);
+ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 644e2d5e3d..5f3b4d9cf5 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -23,7 +23,6 @@
#include <northbridge/amd/nb_common.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <southbridge/amd/pi/hudson/pci_devs.h>
-#include <southbridge/amd/pi/hudson/ioapic.h>
#include <amdblocks/cpu.h>
#define MAX_NODE_NUMS MAX_NODES
@@ -222,7 +221,7 @@ static void nb_set_resources(struct device *dev)
static void northbridge_init(struct device *dev)
{
- setup_ioapic((u8 *)IO_APIC2_ADDR, GNB_IOAPIC_ID);
+ register_new_ioapic((u8 *)IO_APIC2_ADDR);
}
static unsigned long acpi_fill_hest(acpi_hest_t *hest)
@@ -254,17 +253,16 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS |
IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS |
IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS;
- ivhd_ioapic->handle = FCH_IOAPIC_ID;
+ ivhd_ioapic->handle = get_ioapic_id(VIO_APIC_VADDR);
ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC);
ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
current += sizeof(ivrs_ivhd_special_t);
ivhd_ioapic = (ivrs_ivhd_special_t *)current;
-
ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV;
ivhd_ioapic->reserved = 0x0000;
ivhd_ioapic->dte_setting = 0x00;
- ivhd_ioapic->handle = GNB_IOAPIC_ID;
+ ivhd_ioapic->handle = get_ioapic_id((u8 *)IO_APIC2_ADDR);
ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1);
ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
current += sizeof(ivrs_ivhd_special_t);
diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c
index 0693a5d93c..9128c2427e 100644
--- a/src/northbridge/amd/pi/00730F01/state_machine.c
+++ b/src/northbridge/amd/pi/00730F01/state_machine.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/biosram.h>
+#include <amdblocks/ioapic.h>
#include "Porting.h"
#include "AGESA.h"
@@ -9,7 +10,6 @@
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/nb_common.h>
-#include <southbridge/amd/pi/hudson/ioapic.h>
void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{