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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-29 07:03:37 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-01 01:55:01 +0000
commit9137cbd5e4bc7040282ce9eb6fb75e8f251bcffa (patch)
treee2b200a4c62ded5c65b79917a2f348ac5c2498f9 /src/northbridge
parent444d2af9a9b99244967dba978325f2d3bc4dfeb1 (diff)
intel/i945: Delay bridge VGA IO enable to ramstage
Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/early_init.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 791baecc6a..c53577b40d 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -661,11 +661,6 @@ static void i945_setup_pci_express_x16(void)
reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN);
reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);
pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32);
-
- /* Set VGA enable bit in PCIe bridge */
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL);
- reg16 |= PCI_BRIDGE_CTL_VGA;
- pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
}
/* Enable GPEs */