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authorAngel Pons <th3fanbus@gmail.com>2020-08-03 15:47:30 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 21:27:31 +0000
commit90de10c17a2d72065592875b4af206e9cb1a7feb (patch)
tree12a6bdbadef239cbb880737aaa51fee105b791e7 /src/northbridge
parent653d8717ba8d785af4e4eafca2416e1da2988f5d (diff)
nb/intel/pineview: Refactor `decode_pcie_bar`
Constify and eliminate local variables where possible to ease reading. Tested with BUILD_TIMELESS, Foxconn D41S remains identical. Change-Id: Iaad759886a8f5ac07aabdea8ab1c6d1aa7020dfc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/pineview/memmap.c14
1 files changed, 5 insertions, 9 deletions
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index ab0f31bc69..146fff2136 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -19,11 +19,7 @@ int decode_pcie_bar(u32 *const base, u32 *const len)
{
*base = 0;
*len = 0;
- const pci_devfn_t dev = HOST_BRIDGE;
- u32 pciexbar = 0;
- u32 pciexbar_reg;
- u32 reg32;
- int max_buses;
+
const struct {
u16 num_buses;
u32 addr_mask;
@@ -34,7 +30,7 @@ int decode_pcie_bar(u32 *const base, u32 *const len)
{0, 0},
};
- pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+ const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, PCIEXBAR);
/* MMCFG not supported or not enabled */
if (!(pciexbar_reg & (1 << 0))) {
@@ -42,9 +38,9 @@ int decode_pcie_bar(u32 *const base, u32 *const len)
return 0;
}
- reg32 = (pciexbar_reg >> 1) & 3;
- pciexbar = pciexbar_reg & busmask[reg32].addr_mask;
- max_buses = busmask[reg32].num_buses;
+ const u32 index = (pciexbar_reg >> 1) & 3;
+ const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
+ const int max_buses = busmask[index].num_buses;
if (!pciexbar) {
printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");