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| author | Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> | 2017-02-24 15:37:30 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-10 11:11:13 +0100 |
| commit | 6dd7b402d512d5bfc5f3bc20b0fc8c80aca817db (patch) | |
| tree | b9de747f9ae9be9dacb1999894dd3f3dd7839b87 /src/northbridge | |
| parent | d4f92fa603ee7156cb96cb4f1f5f2177b8323ee4 (diff) | |
soc/intel/apollolake: Add PM methods to power gate SD card
This implements dynamic generation of sdcard GpioInt in SSDT.
GpioInt in SSDT generation is based on the card detect GPIO if
it is provided by the mainboard in devicetree.
This implements GNVS variable to store the address of sdcard cd pin.
GNVS used to store rxstate of the sdcard cd pin to get card presence.
Add _PS0/_PS3 methods to power gate the sd card controller in
S0ix and runtime PM.
CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should enter S0ix and resume with no issue.
Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18496
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions