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authorAngel Pons <th3fanbus@gmail.com>2022-11-02 01:04:24 +0100
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2022-11-03 02:01:14 +0000
commit6397687940f899552c37e77c71d4fe4dd04825ad (patch)
tree30193763a9bce0fc3fdac109ad33269e42895749 /src/northbridge
parent5faaca09b8ea433a42a15408ec55074d7f9e143e (diff)
nb/intel/gm45: Make polling loops more explicit
Replace `while (...);` with `do {} while (...);` so that it's easier to distinguish polling loops from something else, like function calls. The `{}` can be understood as "nothing", so that the construct is naturally read as "do nothing while (...)". Another reason to prefer this method is that Jenkins does not complain. Change-Id: Ifbf3cf072f8b817b2fdeece4ef89bae0822bb6e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/gm45/pcie.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 295bf5b0c9..59a49929d7 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -33,12 +33,12 @@ static void init_egress(void)
epbar_write32(EP_PORTARB(7), 0x00005555);
epbar_setbits32(EPVC1RCTL, 1 << 16);
- while ((epbar_read8(EPVC1RSTS) & 1) != 0);
+ do {} while ((epbar_read8(EPVC1RSTS) & 1) != 0);
/* VC1: enable */
epbar_setbits32(EPVC1RCTL, 1 << 31);
- while ((epbar_read8(EPVC1RSTS) & 2) != 0);
+ do {} while ((epbar_read8(EPVC1RSTS) & 2) != 0);
}
/* MCH side */
@@ -56,7 +56,7 @@ static void init_dmi(int b2step)
/* VC1: enable */
dmibar_setbits32(DMIVC1RCTL, 1 << 31);
- while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0);
+ do {} while ((dmibar_read8(DMIVC1RSTS) & VC1NP) != 0);
/* additional configuration. */
dmibar_setbits32(0x200, 3 << 13);