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| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2013-05-17 17:25:25 +0200 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-05-23 10:44:36 +0200 |
| commit | 51837f9dac3cf688a40b6d70ebc56d2f3913c5f4 (patch) | |
| tree | 7750d14ac03964b26d803503767e1537ff1eb1ba /src/northbridge | |
| parent | 1e24f4b37ff4bef3b3130b5399f6302cafa5f555 (diff) | |
Intel Sandy Bridge: udelay.c: Change comparison from <= to <
Currently code in `udelay.c` differs between the Intel northbridges
GM45, 945 on the one hand and Sandy Bridge on the other hand.
The reason for this is that a wrong comparison > was used.
The following commit
commit 784ffb3db694dd2c964d9a4e1c6657a835b2d141
Author: Sven Schnelle <svens@stackframe.org>
Date: Tue Jan 10 12:16:38 2012 +0100
i945: fix tsc udelay()
Reviewed-on: http://review.coreboot.org/530
fixed the sign from > to <, whereas Stefan Reinauer changed it from
> to <= before adding the Sandy Bridge port in the following commit.
commit 00636b0daefc3c499990744226a0e1a316d71731
Author: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date: Wed Apr 4 00:08:51 2012 +0200
Add support for Intel Sandybridge CPU (northbridge part)
Reviewed-on: http://review.coreboot.org/854
As there are no technical reasons for this difference, unify this
between the chipsets. See the discussion of the other patch set in
Gerrit [1].
[1] http://review.coreboot.org/#/c/3220/1/src/northbridge/intel/i5000/udelay.c
Change-Id: I64f2aa1db114ad2e9f34181c5f3034f6a8414a11
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3259
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/udelay.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 3edd69d8d8..01d7abd74c 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -64,5 +64,5 @@ void udelay(u32 us) do { tsc = rdtsc(); } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo))); + || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); } |