diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-11-22 20:36:58 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-12-03 21:02:12 +0100 |
| commit | 4aad743434516d6c96f1afe21dd00b631e2c3692 (patch) | |
| tree | f895dcff92712dd51af55fae3d71feeceb644e1b /src/northbridge | |
| parent | a234f45601e6e85a5179ec9cc446f070b86f425b (diff) | |
i82801gx: Enable upper CMOS in bootblock.
Otherwise checksum may not work correctly on early stages.
For compatibility with old bootblocks also enable it early in romstage.
Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7556
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ffdf6a38..b12ad3a63e 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -171,6 +171,9 @@ static void i945_setup_bars(void) outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |