diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2018-10-01 19:17:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:35:25 +0000 |
| commit | 45022ae056cdbf58429b77daf2da176306312801 (patch) | |
| tree | 4218666e3c14e41232778c4ceff301292b3c61d9 /src/northbridge | |
| parent | 33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff) | |
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index 999d5a812e..fcba7c1457 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -19,12 +19,12 @@ #include <console/console.h> #include <bootstate.h> #include <cbmem.h> +#include <cf9_reset.h> #include <device/device.h> #include <southbridge/intel/fsp_rangeley/pci_devs.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <fspvpd.h> #include <fspbootmode.h> -#include <reset.h> #include "../chip.h" #ifdef __PRE_RAM__ @@ -173,7 +173,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; if (Status == 0xFFFFFFFF) { - soft_reset(); + system_reset(); } romstage_main_continue(Status, HobListPtr); } diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index eb316555fb..24fdc7497b 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -18,11 +18,11 @@ #include <console/console.h> #include <bootstate.h> #include <cbmem.h> +#include <cf9_reset.h> #include <device/device.h> #include <southbridge_pci_devs.h> #include <fsp_util.h> #include "../chip.h" -#include <reset.h> #ifdef __PRE_RAM__ @@ -97,7 +97,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, { *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; if (Status == 0xFFFFFFFF) { - hard_reset(); + system_reset(); } romstage_main_continue(Status, HobListPtr); } |