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authorAngel Pons <th3fanbus@gmail.com>2021-09-08 15:23:22 +0200
committerMatt DeVillier <matt.devillier@gmail.com>2024-04-16 01:46:42 +0000
commit41d107019b6bcbdad80a1d76abca7a181fd339d5 (patch)
treea61c836cb2f7f3eed815ae340de95ad5e92cbdc9 /src/northbridge
parent6ef23316c235d14213d0bdc48c6853d3059a0b64 (diff)
sb/intel/lynxpoint: Fix AER and L1 sub-state reporting
Program the AER capability header register in a single write because it's write-once. In addition, only PCH-LP supports L1 sub-states, so only report the L1 sub-state capability on PCH-LP. This follows what Lynx Point PCH reference code version 1.9.1 does. Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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