x86: Unify arch/io.h and arch/romcc_io.h

Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

38 files changed, 11 insertions, 39 deletions

diff --git a/src/northbridge/amd/amdfam10/bootblock.c b/src/northbridge/amd/amdfam10/bootblock.c
index 612004a7eb..de1b7d1907 100644
--- a/src/northbridge/amd/amdfam10/bootblock.c
+++ b/src/northbridge/amd/amdfam10/bootblock.c
@@ -1,5 +1,4 @@
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include "northbridge/amd/amdfam10/early_ht.c"
 
diff --git a/src/northbridge/amd/amdk8/bootblock.c b/src/northbridge/amd/amdk8/bootblock.c
index b5395bbd9f..3a185a6581 100644
--- a/src/northbridge/amd/amdk8/bootblock.c
+++ b/src/northbridge/amd/amdk8/bootblock.c
@@ -1,5 +1,4 @@
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include "northbridge/amd/amdk8/early_ht.c"
 
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 9ad342367c..22d74c2c16 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -67,7 +67,7 @@
 #include <device/pci_ids.h>
 #include <device/hypertransport_def.h>
 #include <stdlib.h>
-#include "arch/romcc_io.h"
+#include <arch/io.h>
 #include <pc80/mc146818rtc.h>
 #if CONFIG_HAVE_OPTION_TABLE
 #include "option_table.h"
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index 87569a5981..3d6ca2a25e 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -3,7 +3,6 @@
 #include <console/console.h>
 #include <stdlib.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <spd.h>
 
 #include "raminit.h"
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 9fba602833..ae02a7c3d0 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -15,7 +15,6 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <stdlib.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 09a166d82f..052c517781 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include "gm45.h"
 
 void gm45_early_init(void)
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index f3902beb5d..fccb97f612 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -21,7 +21,6 @@
 
 #include <types.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include "gm45.h"
 
 void gm45_early_reset(void/*const timings_t *const timings*/)
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index c07fdfc26b..d54ee41f83 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -22,7 +22,6 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 89770ee71b..e40954adec 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -23,7 +23,6 @@
 #include <string.h>
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <arch/acpi.h>
 
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 6b42e15d0c..39791a62b8 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -23,7 +23,6 @@
 #include <stddef.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c
index 32a5ba7b96..b9ac7f05f1 100644
--- a/src/northbridge/intel/gm45/pm.c
+++ b/src/northbridge/intel/gm45/pm.c
@@ -23,7 +23,6 @@
 #include <stddef.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <console/console.h>
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 1da9e87ed1..9e54c10000 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -19,9 +19,11 @@
  * MA 02110-1301 USA
  */
 
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "gm45.h"
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 68c81206e1..d607f84e10 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -22,7 +22,6 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <spd.h>
diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c
index a74bcc5e61..c2ab2a5f85 100644
--- a/src/northbridge/intel/gm45/thermal.c
+++ b/src/northbridge/intel/gm45/thermal.c
@@ -23,7 +23,6 @@
 #include <stddef.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <spd.h>
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index 35f357f57f..743007e157 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -1,5 +1,4 @@
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 
 /* Just re-define this instead of including haswell.h. It blows up romcc. */
 #define PCIEXBAR	0x60
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index a94c0ce6f0..5b364189e9 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -22,7 +22,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include "haswell.h"
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c
index 58052f9952..457f4af0fb 100644
--- a/src/northbridge/intel/haswell/finalize.c
+++ b/src/northbridge/intel/haswell/finalize.c
@@ -19,7 +19,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <stdlib.h>
 #include "haswell.h"
 
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 1439200de9..9a9bb1c09f 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -21,7 +21,6 @@
 #include <string.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
 #include <cbfs.h>
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 9a141b6940..8bb4a05fbc 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -22,9 +22,7 @@
 #include <string.h>
 #include "southbridge/intel/lynxpoint/pch.h"
 #include <arch/io.h>
-#include <arch/io.h>
 #include <cpu/x86/msr.h>
-#include <arch/romcc_io.h>
 #include "haswell.h"
 
 static void report_cpu_info(void)
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index ef2f45c4da..ef9d51382a 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -1,6 +1,5 @@
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <spd.h>
 #include "raminit.h"
 #include <spd.h>
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 7472cc994b..e3cfbdf256 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -24,7 +24,6 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "i440bx.h"
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index 3c913cf66c..48499da4f3 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -21,7 +21,6 @@
 
 #include "raminit.h"
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h
index d3fa16a6ef..aa140928db 100644
--- a/src/northbridge/intel/i5000/raminit.h
+++ b/src/northbridge/intel/i5000/raminit.h
@@ -24,7 +24,6 @@
 
 #include <types.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 
 #define I5000_MAX_BRANCH 2
 #define I5000_MAX_CHANNEL 2
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index 88adc24ab1..c3e4fb99e6 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -1,6 +1,5 @@
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <spd.h>
 #include "i82810.h"
 #include "raminit.h"
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 6a85221d7f..2c379e7865 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -24,7 +24,6 @@
 #include <delay.h>
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "i82810.h"
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index 37b138a6da..e4d93cfe69 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -22,7 +22,6 @@
 #include <types.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 859a1ef613..e47f762fb6 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -22,7 +22,6 @@
 #include <spd.h>
 #include <lib.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "i945.h"
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 12e320b834..d91930fe16 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -21,7 +21,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include "i945.h"
 #include "pcie_config.c"
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index bbd652820f..b1a0684b8e 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -23,7 +23,7 @@
 #include <pc80/mc146818rtc.h>
 #include <spd.h>
 #include <string.h>
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 #include "raminit.h"
 #include "i945.h"
 #include <cbmem.h>
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index fc10d34dd2..c2d4909f06 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -22,7 +22,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include "sandybridge.h"
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
index 81512e7e63..0fa8d1a8a4 100644
--- a/src/northbridge/intel/sandybridge/finalize.c
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -19,7 +19,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <stdlib.h>
 #include "pcie_config.c"
 #include "sandybridge.h"
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 7597b0258d..78eedb89db 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -21,7 +21,6 @@
 #include <string.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
 #include <cbfs.h>
diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c
index 6e96c94d0a..cc748415f9 100644
--- a/src/northbridge/intel/sandybridge/report_platform.c
+++ b/src/northbridge/intel/sandybridge/report_platform.c
@@ -22,7 +22,6 @@
 #include <string.h>
 #include "southbridge/intel/bd82x6x/pch.h"
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include "sandybridge.h"
 
 static void report_cpu_info(void)
diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c
index d3ba70db03..c73f7098e7 100644
--- a/src/northbridge/intel/sch/port_access.c
+++ b/src/northbridge/intel/sch/port_access.c
@@ -17,9 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
diff --git a/src/northbridge/via/cx700/early_serial.c b/src/northbridge/via/cx700/early_serial.c
index cde0b31dc5..ae59295200 100644
--- a/src/northbridge/via/cx700/early_serial.c
+++ b/src/northbridge/via/cx700/early_serial.c
@@ -21,7 +21,7 @@
  * Enable the serial devices on the VIA CX700
  */
 
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 static void cx700_writepnpaddr(u8 val)
 {
diff --git a/src/northbridge/via/vx800/early_serial.c b/src/northbridge/via/vx800/early_serial.c
index b6f58ac580..b3ebde1433 100644
--- a/src/northbridge/via/vx800/early_serial.c
+++ b/src/northbridge/via/vx800/early_serial.c
@@ -20,7 +20,7 @@
 /*
  * Enable the serial devices on the VIA
  */
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 /* The base address is 0x15c, 0x2e, depending on config bytes */
 
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c
index 228cc7e3cd..7c3fb7ae87 100644
--- a/src/northbridge/via/vx800/examples/romstage.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "console/console.c"
 #include "lib/ramtest.c"
diff --git a/src/northbridge/via/vx800/pci_rawops.h b/src/northbridge/via/vx800/pci_rawops.h
index 8e775607bc..33eebc40ac 100644
--- a/src/northbridge/via/vx800/pci_rawops.h
+++ b/src/northbridge/via/vx800/pci_rawops.h
@@ -22,7 +22,7 @@
 #define NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H
 
 #include <stdint.h>
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 struct VIA_PCI_REG_INIT_TABLE {
 	u8 ChipRevisionStart;