diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-18 17:48:40 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-06 16:18:31 +0000 |
| commit | 1bb327f2162d4ce736a632ef817e48622ae9dbc1 (patch) | |
| tree | 843b7d17e901c1d18e139096a8382d0f82a3c08f /src/northbridge | |
| parent | e8f62d1355fbe912cf874e18853be45da2ec0217 (diff) | |
sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree
Since the SMBus controller in the PCH is always on the same device
function, the device operations can be statically assigned in the
devicetree and there's no need to bind the SMBus device operations to
the PCI device during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3d3745ba5aefa30efbe705155d216aa7eadd26a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79168
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chipset.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 83680c12e9..15be1b0eb2 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -39,7 +39,7 @@ chip northbridge/intel/sandybridge device pci 1e.0 alias pci_bridge off end # PCI bridge device pci 1f.0 alias lpc on ops bd82x6x_lpc_bridge_ops end device pci 1f.2 alias sata1 off end # SATA Controller 1 - device pci 1f.3 alias smbus on end # SMBus + device pci 1f.3 alias smbus on ops bd82x6x_smbus_ops end device pci 1f.5 alias sata2 off end # SATA Controller 2 device pci 1f.6 alias thermal off end # Thermal end |