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authorEran Mitrani <mitrani@google.com>2022-11-29 12:54:53 -0800
committerFelix Held <felix-coreboot@felixheld.de>2022-12-02 14:48:37 +0000
commit13e151f31ce25dce4116214d7e3329506e029887 (patch)
tree3a16064789c8abd372b2f762f93ec10d6d92f769 /src/northbridge
parent50a32650172dfedc2a6c5335af94fb2d3c7d71e6 (diff)
soc/intel/alderlake: skip external buses for D-states list
The devices in the list that was introduced in commit c66ea985776 ("soc/intel/alderlake: provide a list of D-states to enter LPM") are all internal. This CL skips the external buses (which caused the addition of packages to non-existant paths such as "_SB.PCI0.RP1.MCHC", and warnings from the kernel) BUG=b:231582182 TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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