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authorFurquan Shaikh <furquan@chromium.org>2017-03-31 17:10:02 -0700
committerFurquan Shaikh <furquan@google.com>2017-04-06 00:45:11 +0200
commit108f87262bf47ce3549fa0c5ed16a40fe916656f (patch)
treecf982de0bd09d7d9e3c06903355cddbe52404141 /src/northbridge
parent340908aecf01093d35aaf0b71c55ed65c3ebbeac (diff)
soc/intel/common: Add support for common GSPI controller
Add support for GSPI controller in Intel PCH. This controller is compliant with PXA2xx SPI controller with some additional registers to provide more fine-grained control of the SPI bus. Currently, DMA is not enabled as this driver might be used before memory is up (e.g. TPM on SPI). Also, provide common GSPI config structure that can be included by SoCs in chip config to allow mainboards to configure GSPI bus. Additionally, provide an option for SoCs to configure BAR for GSPI controllers before memory is up. BUG=b:35583330 Change-Id: I0eb91eba2c523be457fee8922c44fb500a9fa140 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19098 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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