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authorStefan Reinauer <stefan.reinauer@coreboot.org>2016-02-24 14:01:59 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2016-03-13 02:22:39 +0100
commit2510e2aa448dd7eb52232fa65def0be16af5da84 (patch)
treefbf906ed0261767fb6f0ff6a18a8e3f37cc1a392 /src/northbridge
parente3fd63f264e1f6e2869cf5868e1810dff5641147 (diff)
northbridge/intel/i3100: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i3100 boards in the chipset. Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13786 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i3100/Kconfig1
-rw-r--r--src/northbridge/intel/i3100/raminit_ep80579.c1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig
index cb0bd38086..2260664129 100644
--- a/src/northbridge/intel/i3100/Kconfig
+++ b/src/northbridge/intel/i3100/Kconfig
@@ -1,6 +1,7 @@
config NORTHBRIDGE_INTEL_I3100
bool
select LATE_CBMEM_INIT
+ select UDELAY_IO
if NORTHBRIDGE_INTEL_I3100
config DIMM_MAP_LOGICAL
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 7996e111bc..497339c0e7 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -19,6 +19,7 @@
#include <cpu/x86/cache.h>
#include <cpu/intel/speedstep.h>
#include <lib.h>
+#include <delay.h>
#include "raminit_ep80579.h"
#include "ep80579.h"