northbridge/via: Add space around operators

Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16623
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

7 files changed, 119 insertions, 119 deletions

diff --git a/src/northbridge/via/vx800/dev_init.c b/src/northbridge/via/vx800/dev_init.c
index 819605018e..7cd557a02c 100644
--- a/src/northbridge/via/vx800/dev_init.c
+++ b/src/northbridge/via/vx800/dev_init.c
@@ -38,13 +38,13 @@ static const u8 DramRegTbl[][3] = {
 	/* Reg AND   OR */
 	{0x50, 0x11, 0xEE},	// DDR default MA7 for DRAM init
 	{0x51, 0x11, 0x60},	// DDR default MA3 for CHB init
-	{0x52, 0x00, 0x33},	// DDR use BA0=M17, BA1=M18,
-	{0x53, 0x00, 0x3F},	// DDR    BA2=M19
+	{0x52, 0x00, 0x33},	// DDR use BA0 = M17, BA1 = M18,
+	{0x53, 0x00, 0x3F},	// DDR     BA2 = M19
 
-	{0x54, 0x00, 0x00},	// default PR0=VR0; PR1=VR1
-	{0x55, 0x00, 0x00},	// default PR2=VR2; PR3=VR3
-	{0x56, 0x00, 0x00},	// default PR4=VR4; PR5=VR5
-	{0x57, 0x00, 0x00},	// default PR4=VR4; PR5=VR5
+	{0x54, 0x00, 0x00},	// default PR0 = VR0; PR1 = VR1
+	{0x55, 0x00, 0x00},	// default PR2 = VR2; PR3 = VR3
+	{0x56, 0x00, 0x00},	// default PR4 = VR4; PR5 = VR5
+	{0x57, 0x00, 0x00},	// default PR4 = VR4; PR5 = VR5
 
 	{0x60, 0x00, 0x00},	// disable fast turn-around
 	{0x65, 0x00, 0xD9},	// AGP timer = 0XD; Host timer = 8;
@@ -317,15 +317,15 @@ Purpose   : Initialize DDR2 by standard sequence
 ===================================================================*/
 
 //                               DLL:         Enable                              Reset
-static const u32 CHA_MRS_DLL_150[2] = { 0x00020200, 0x00000800 };	// with 150 ohm (A17=1, A9=1), (A11=1)(cpu address)
-static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 };	// with 75 ohm  (A17=1, A5=1), (A11=1)(cpu address)
+static const u32 CHA_MRS_DLL_150[2] = { 0x00020200, 0x00000800 };	// with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address)
+static const u32 CHA_MRS_DLL_75[2] = { 0x00020020, 0x00000800 };	// with 75 ohm  (A17 = 1, A5 = 1), (A11 = 1)(cpu address)
 
 //               CPU(DRAM)
 // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 }
 // { DLL: reset.  A11(MA8)=1 }
 //
-//                      DDR2                    CL=2    CL=3    CL=4    CL=5     CL=6(Burst type=interleave)(WR fine tune in code)
-static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 };	// BL=4 ;Use 1X-bandwidth MA table to init DRAM
+//                      DDR2                    CL = 2    CL = 3    CL = 4    CL = 5     CL = 6(Burst type = interleave)(WR fine tune in code)
+static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350 };	// BL = 4 ;Use 1X-bandwidth MA table to init DRAM
 
 //                                                       MA11        MA10(AP)      MA9
 #define CHA_MRS_DDR2_TWR2		(0 << 13) + (0 << 20) + (1 << 12)	// Value = 001000h
@@ -334,20 +334,20 @@ static const u16 CHA_DDR2_MRS_table[5] = { 0x0150, 0x01D0, 0x0250, 0x02D0, 0x350
 #define CHA_MRS_DDR2_TWR5		(1 << 13) + (0 << 20) + (0 << 12)	// Value = 002000h
 #define CHA_MRS_DDR2_TWR6		(1 << 13) + (0 << 20) + (1 << 12)	// Value = 003000h
 
-//                              DDR2             Twr=2                  Twr=3              Twr=4                  Twr=5
+//                              DDR2             Twr = 2                  Twr = 3              Twr = 4                  Twr = 5
 static const u32 CHA_DDR2_Twr_table[5] = {
 	CHA_MRS_DDR2_TWR2, CHA_MRS_DDR2_TWR3, CHA_MRS_DDR2_TWR4,
 	CHA_MRS_DDR2_TWR5, CHA_MRS_DDR2_TWR6
 };
 
-#define CHA_OCD_Exit_150ohm		0x20200	// EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address)
-//                A17=1, A12=A11=A10=0,A9=1 ,A5=0  (CPU address)
-#define CHA_OCD_Default_150ohm		0x21E00	// EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address)
-//               A17=1, A12=A11=A10=1,A9=1 ,A5=0  (CPU address)
-#define CHA_OCD_Exit_75ohm		0x20020	// EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address)
-//              A17=1, A12=A11=A10=0,A9=0 ,A5=1  (CPU address)
-#define CHA_OCD_Default_75ohm		0x21C20	// EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address)
-//              A17=1, A12=A11=A10=1,A9=0 ,A5=1  (CPU address)
+#define CHA_OCD_Exit_150ohm		0x20200	// EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address)
+//                A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0  (CPU address)
+#define CHA_OCD_Default_150ohm		0x21E00	// EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address)
+//               A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0  (CPU address)
+#define CHA_OCD_Exit_75ohm		0x20020	// EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address)
+//              A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1  (CPU address)
+#define CHA_OCD_Default_75ohm		0x21C20	// EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address)
+//              A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1  (CPU address)
 
 void InitDDR2CHA(DRAM_SYS_ATTR *DramAttr)
 {
@@ -527,14 +527,14 @@ Purpose   : Initialize DDR2 of CHB by standard sequence
 Reference  :
 ===================================================================*/
 /*//		                 DLL:	      Enable				  Reset
-static const  u32 CHB_MRS_DLL_150[2] =	{ 0x00020200 | (1 << 20), 0x00000800 };	// with 150 ohm (A17=1, A9=1), (A11=1)(cpu address)
-//u32 CHB_MRS_DLL_75[2]  =	{ 0x00020020 | (1 << 20), 0x00000800 };	// with 75 ohm  (A17=1, A5=1), (A11=1)(cpu address)
+static const  u32 CHB_MRS_DLL_150[2] =	{ 0x00020200 | (1 << 20), 0x00000800 };	// with 150 ohm (A17 = 1, A9 = 1), (A11 = 1)(cpu address)
+//u32 CHB_MRS_DLL_75[2]  =	{ 0x00020020 | (1 << 20), 0x00000800 };	// with 75 ohm  (A17 = 1, A5 = 1), (A11 = 1)(cpu address)
 //		 CPU(DRAM)
 // { DLL: Enable. A17(BA0)=1 and A3(MA0)=0 }
 // { DLL: reset.  A11(MA8)=1 }
 //
-//                      DDR2 			CL=2	CL=3	CL=4	CL=5 	(Burst type=interleave)(WR fine tune in code)
-static const  u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 };	// BL=4 ;Use 1X-bandwidth MA table to init DRAM
+//                      DDR2 			CL = 2	CL = 3	CL = 4	CL = 5 	(Burst type = interleave)(WR fine tune in code)
+static const  u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 };	// BL = 4 ;Use 1X-bandwidth MA table to init DRAM
 
 //			 				 MA11	     MA10(AP)      MA9
 #define CHB_MRS_DDR2_TWR2		(0 << 13) + (0 << 20) + (1 << 12)	// Value = 001000h
@@ -543,17 +543,17 @@ static const  u16 CHB_DDR2_MRS_table[4] ={ 0x0150, 0x01D0, 0x0250, 0x02D0 };	//
 #define CHB_MRS_DDR2_TWR5		(1 << 13) + (0 << 20) + (0 << 12)	// Value = 002000h
 #define CHB_MRS_DDR2_TWR6		(1 << 13) + (0 << 20) + (1 << 12)	// Value = 003000h
 
-//				DDR2 		 Twr=2			Twr=3		   Twr=4		  Twr=5
+//				DDR2 		 Twr = 2			Twr = 3		   Twr = 4		  Twr = 5
 static const u32 CHB_DDR2_Twr_table[5] = { CHB_MRS_DDR2_TWR2,	CHB_MRS_DDR2_TWR3, CHB_MRS_DDR2_TWR4, CHB_MRS_DDR2_TWR5, CHB_MRS_DDR2_TWR6 };
 
-#define CHB_OCD_Exit_150ohm		0x20200 | (1 << 20) 		 // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=1,MA2=0 (DRAM bus address)
-//	          A17=1, A12=A11=A10=0,A9=1 ,A5=0  (CPU address)
-#define CHB_OCD_Default_150ohm	0x21E00 | (1 << 20)     	// EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=1,MA2=0 (DRAM bus address)
-//	         A17=1, A12=A11=A10=1,A9=1 ,A5=0  (CPU address)
-//#define CHB_OCD_Exit_75ohm		0x20020 | (1 << 20) 	      // EMRS(1), BA0=1, MA9=MA8=MA7=0,MA6=0,MA2=1 (DRAM bus address)
-//	        A17=1, A12=A11=A10=0,A9=0 ,A5=1  (CPU address)
-//#define CHB_OCD_Default_75ohm	0x21C20 | (1 << 20)      // EMRS(1), BA0=1, MA9=MA8=MA7=1,MA6=0,MA2=1 (DRAM bus address)
-//	        A17=1, A12=A11=A10=1,A9=0 ,A5=1  (CPU address)
+#define CHB_OCD_Exit_150ohm		0x20200 | (1 << 20) 		 // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 1,MA2 = 0 (DRAM bus address)
+//	          A17 = 1, A12 = A11 = A10 = 0,A9 = 1 ,A5 = 0  (CPU address)
+#define CHB_OCD_Default_150ohm	0x21E00 | (1 << 20)     	// EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 1,MA2 = 0 (DRAM bus address)
+//	         A17 = 1, A12 = A11 = A10 = 1,A9 = 1 ,A5 = 0  (CPU address)
+//#define CHB_OCD_Exit_75ohm		0x20020 | (1 << 20) 	      // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 0,MA6 = 0,MA2 = 1 (DRAM bus address)
+//	        A17 = 1, A12 = A11 = A10 = 0,A9 = 0 ,A5 = 1  (CPU address)
+//#define CHB_OCD_Default_75ohm	0x21C20 | (1 << 20)      // EMRS(1), BA0 = 1, MA9 = MA8 = MA7 = 1,MA6 = 0,MA2 = 1 (DRAM bus address)
+//	        A17 = 1, A12 = A11 = A10 = 1,A9 = 0 ,A5 = 1  (CPU address)
 void InitDDR2CHB(
                DRAM_SYS_ATTR          *DramAttr
              )
@@ -568,27 +568,27 @@ void InitDDR2CHB(
 
     // step3.
     //disable bank paging and multi page
-    Data=pci_read_config8(MEMCTRL, 0x69);
+    Data = pci_read_config8(MEMCTRL, 0x69);
     Data &= ~0x03;
     pci_write_config8(MEMCTRL, 0x69, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data |= 0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
     //step 4. Initialize CHB begin
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data |= 0x40;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
     //Step 5. NOP command enable
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data  |= 0x08;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
     //Step 6.  issue a nop cycle,RegD3[7]  0 -> 1
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
@@ -603,25 +603,25 @@ void InitDDR2CHB(
 
     // Step 8.
     // all banks precharge command enable
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data |= 0x10;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
    //step 9. issue a precharge all cycle,RegD3[7]  0 -> 1
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
    //step10. EMRS enable
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data |= 0x18;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0xC7;
     Data |= 0x08;
     pci_write_config8(MEMCTRL, 0xd3, Data);
@@ -634,25 +634,25 @@ void InitDDR2CHB(
     Data = (u8)((AccessAddr & 0xff00) >> 8);
     pci_write_config8(MEMCTRL, 0xda, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xF9;
     Data |= (u8)((AccessAddr & 0x30000) >> 15);
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
     //step12.  issue EMRS cycle
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
     //step13. MSR enable
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data |= 0x18;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0xC7;
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd3, Data);
@@ -665,13 +665,13 @@ void InitDDR2CHB(
     Data = (u8)((AccessAddr & 0xff00) >> 8);
     pci_write_config8(MEMCTRL, 0xda, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xF9;
     Data |= (u8)((AccessAddr & 0x30000) >> 15);
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
     //step15.  issue MRS cycle
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
@@ -682,21 +682,21 @@ void InitDDR2CHB(
     pci_write_config8(MEMCTRL, 0xda, Data);
 
      //step16.  all banks precharge command enable
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data |= 0x10;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
 
    // step17. issue precharge all cycle
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
     //step18.  CBR cycle enable
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data |= 0x20;
     pci_write_config8(MEMCTRL, 0xd7, Data);
@@ -706,7 +706,7 @@ void InitDDR2CHB(
     for (Idx = 0; Idx < 8; Idx++)
     {
          // issue CBR cycle
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
@@ -716,12 +716,12 @@ void InitDDR2CHB(
     }
 
     //step22. MSR enable
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data |= 0x18;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0xC7;
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd3, Data);
@@ -730,11 +730,11 @@ void InitDDR2CHB(
     //the SDRAM parameters.(Burst Length, CAS# Latency , Write recovery etc.)
     //-------------------------------------------------------------
     //Burst Length : really offset Rx6c[1]
-    Data=pci_read_config8(MEMCTRL, 0x6C);
+    Data = pci_read_config8(MEMCTRL, 0x6C);
     BL = (Data & 0x02) >> 1;
 
     // CL = really offset RX62[2:0]
-    Data=pci_read_config8(MEMCTRL, 0x62);
+    Data = pci_read_config8(MEMCTRL, 0x62);
     CL = Data & 0x03;
 
     AccessAddr  = (u32)(CHB_DDR2_MRS_table[CL]);
@@ -744,7 +744,7 @@ void InitDDR2CHB(
     }
 
     //Write recovery  : really offset Rx63[7:5]
-    Data=pci_read_config8(MEMCTRL, 0x63);
+    Data = pci_read_config8(MEMCTRL, 0x63);
     Twr = (Data & 0xE0) >> 5;
 
     AccessAddr += CHB_DDR2_Twr_table[Twr];
@@ -758,25 +758,25 @@ void InitDDR2CHB(
     Data = (u8)((AccessAddr & 0xFF00) >> 8);
     pci_write_config8(MEMCTRL, 0xda, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xF9;
     Data |= (u8)(((AccessAddr & 0x30000)>>16) << 1);
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
      //step 24.  issue MRS cycle
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
     //step 25. EMRS enable
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data |= 0x18;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0xC7;
     Data |= 0x08;
     pci_write_config8(MEMCTRL, 0xd3, Data);
@@ -790,25 +790,25 @@ void InitDDR2CHB(
     Data = (u8)((AccessAddr & 0xff00) >> 8);
     pci_write_config8(MEMCTRL, 0xda, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xF9;
     Data |= (u8)((AccessAddr & 0x30000) >> 15);
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
     //step 27.  issue EMRS cycle
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
      //step 25. EMRS enable
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data |= 0x18;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0xC7;
     Data |= 0x08;
     pci_write_config8(MEMCTRL, 0xd3, Data);
@@ -821,13 +821,13 @@ void InitDDR2CHB(
     Data = (u8)((AccessAddr & 0xff00) >> 8);
     pci_write_config8(MEMCTRL, 0xda, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xF9;
     Data |= (u8)((AccessAddr & 0x30000) >> 15);
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
      //step 29. issue EMRS cycle
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0x7F;
     pci_write_config8(MEMCTRL, 0xd3, Data);
     Data |=  0x80;
@@ -840,29 +840,29 @@ void InitDDR2CHB(
     Data = 0x00;
     pci_write_config8(MEMCTRL, 0xda, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xF9;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
     //step 30. normal SDRAM Mode
-    Data=pci_read_config8(MEMCTRL, 0xd7);
+    Data = pci_read_config8(MEMCTRL, 0xd7);
     Data &= 0xC7;
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd7, Data);
 
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0xC7;
     Data |= 0x00;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
     //step 31.  exit the initialization mode
-    Data=pci_read_config8(MEMCTRL, 0xd3);
+    Data = pci_read_config8(MEMCTRL, 0xd3);
     Data &= 0xBF;
     pci_write_config8(MEMCTRL, 0xd3, Data);
 
 
     //step 32. Enable bank paging and multi page
-    Data=pci_read_config8(MEMCTRL, 0x69);
+    Data = pci_read_config8(MEMCTRL, 0x69);
     Data |= 0x03;
     pci_write_config8(MEMCTRL, 0x69, Data);
 }
@@ -878,7 +878,7 @@ Output     : Void
 Purpose   : Initialize DDR2 of CHC by standard sequence
 Reference  :
 ===================================================================*/
-//                      DDR2                 CL=2          CL=3 CL=4   CL=5     (Burst type=interleave)(WR fine tune in code)
+//                      DDR2                 CL = 2          CL = 3 CL = 4   CL = 5     (Burst type = interleave)(WR fine tune in code)
 static const u16 CHC_MRS_table[4] = { 0x22B, 0x23B, 0x24B, 0x25B };	// Use 1X-bandwidth MA table to init DRAM
 
 void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr)
diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h
index 6fa18779d4..e4e143aa0c 100644
--- a/src/northbridge/via/vx800/dram_init.h
+++ b/src/northbridge/via/vx800/dram_init.h
@@ -75,7 +75,7 @@
 #define SPD_SDRAM_COL_ADDR           4	/*Number of column addresses on this assembly */
 #define SPD_SDRAM_DIMM_RANKS         5	/*Number of RANKS on this assembly */
 #define SPD_SDRAM_MOD_DATA_WIDTH     6	/*Data width of this assembly */
-#define SPD_SDRAM_TCLK_X             9	/*Cycle time at Maximum supported CAS latency (CL=X) */
+#define SPD_SDRAM_TCLK_X             9	/*Cycle time at Maximum supported CAS latency (CL = X) */
 #define SPD_SDRAM_TAC_X              10	/*Access time for highest CL */
 #define SPD_SDRAM_CONFIG_TYPE        11	/*Non-parity , Parity or ECC */
 #define SPD_SDRAM_REFRESH            12	/*Refresh rate/type */
diff --git a/src/northbridge/via/vx800/drdy_bl.c b/src/northbridge/via/vx800/drdy_bl.c
index 634b8a8830..b9466b9813 100644
--- a/src/northbridge/via/vx800/drdy_bl.c
+++ b/src/northbridge/via/vx800/drdy_bl.c
@@ -42,14 +42,14 @@
 //    a.RDRPH(MD        input internal timing control)
 //    b.CAS Latency
 //    RDELAYMD(1bit) = bit0 of (CL + RDRPH)
-//    for example: RDRPH=10b, CL3 -> F3_Rx56[5:4]=11b, 10b + 11b        = 101b, RDELAYMD=1 (bit0)
-//                RDRPH=00b, CL2.5 -> F3_Rx56[5:4]=10b, 00b + 10b = 010b, RDELAYMD=0 (bit0)
+//    for example: RDRPH = 10b, CL3 -> F3_Rx56[5:4]=11b, 10b + 11b        = 101b, RDELAYMD = 1 (bit0)
+//                RDRPH = 00b, CL2.5 -> F3_Rx56[5:4]=10b, 00b + 10b = 010b, RDELAYMD = 0 (bit0)
 // 2. CPU Frequency
 // 3. DRAM Frequency
 //
 // According to above conditions, we create different tables:
-// 1. RDELAYMD=0        : for integer CAS latency(ex. CL=3)
-// 2. RDELAYMD=1        : for non-integer CAS latency(ex. CL=2.5)
+// 1. RDELAYMD = 0        : for integer CAS latency(ex. CL = 3)
+// 2. RDELAYMD = 1        : for non-integer CAS latency(ex. CL = 2.5)
 // 3. Normal performance
 // 4. Top performance :
 //                     Using phase0 to a case has better performance.
@@ -439,7 +439,7 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
 	Data |= 0x08;
 	pci_write_config8(PCI_DEV(0, 0, 2), 0x54, Data);
 
-	//Data=pci_read_config8(PCI_DEV(0,0,2), 0x55);
+	//Data = pci_read_config8(PCI_DEV(0,0,2), 0x55);
 	//Data = Data & (~0x20);
 	//pci_write_config8(PCI_DEV(0,0,2), 0x55, Data);
 
@@ -538,17 +538,17 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr)
 
 /*This routine process the ability for North Bridge side burst functionality
 There are 3 variances that are valid:
-	1. DIMM	BL=8, chipset BL=8
-	2. DIMM	BL=4, chipset BL=4
-	3. DIMM	BL=4, chipset BL=8 (only happened on Dual channel)
+	1. DIMM	BL = 8, chipset BL = 8
+	2. DIMM	BL = 4, chipset BL = 4
+	3. DIMM	BL = 4, chipset BL = 8 (only happened on Dual channel)
      Device 0 function 2 HOST:REG54[4] must be 1 when 128-bit mode.
 Since DIMM will be initialized	in each	rank individually,
-	1.If all DIMM BL=4, DIMM will initialize BL=4 first,
+	1.If all DIMM BL = 4, DIMM will initialize BL = 4 first,
 	  then check dual_channel flag to enable VIA_NB2HOST_REG54[4].
-	2.If all DIMM BL=8, DIMM will initialize BL=8 first,
-	  then check dual_channel flag for re-initialize DIMM BL=4.
+	2.If all DIMM BL = 8, DIMM will initialize BL = 8 first,
+	  then check dual_channel flag for re-initialize DIMM BL = 4.
 	  also VIA_NB2HOST_REG54[4] need	to be enabled.
-Chipset_BL8==>chipset side can	set burst length=8
+Chipset_BL8==>chipset side can	set burst length = 8
 two register need to set
  1. Device 0 function 2 HOST:REG54[4]
  2. Device 0 function 3 DRAM:REG6C[3]
@@ -557,7 +557,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr)
 {
 	u8 Data, BL;
 	u8 Sockets;
-	/*SPD byte16 bit3,2 describes the burst length supported. bit3=1 support BL=8 bit2=1 support BL=4 */
+	/*SPD byte16 bit3,2 describes the burst length supported. bit3 = 1 support BL = 8 bit2 = 1 support BL = 4 */
 	BL = 0x0c;
 	for (Sockets = 0; Sockets < 2; Sockets++) {
 		if (DramAttr->DimmInfo[Sockets].bPresence) {
@@ -568,9 +568,9 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr)
 		}
 	}
 
-	/*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL=4 ; =1 BL=8 */
+	/*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL = 4 ; =1 BL = 8 */
 
-	if (BL & 0x08)		/*All Assembly support BL=8 */
+	if (BL & 0x08)		/*All Assembly support BL = 8 */
 		BL = 0x8;	/*set bit3 */
 	else
 		BL = 0x00;	/*clear bit3 */
@@ -582,7 +582,7 @@ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr)
 	if (DramAttr->RankNumChB > 0) {
 		BL = DramAttr->DimmInfo[2].SPDDataBuf[SPD_SDRAM_BURSTLENGTH];
 		//Rx6c[1], CHB burst length
-		if (BL & 0x08)	/*CHB support BL=8 */
+		if (BL & 0x08)	/*CHB support BL = 8 */
 			BL = 0x2;	/*set bit1 */
 		else
 			BL = 0x00;	/*clear bit1 */
diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c
index dc2e1bd62a..6e11704e28 100644
--- a/src/northbridge/via/vx800/freq_setting.c
+++ b/src/northbridge/via/vx800/freq_setting.c
@@ -196,13 +196,13 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr)
 	}
 
 	/* cycle time value
-	   0x25-->2.5ns Freq=400  DDR800
-	   0x30-->3.0ns Freq=333  DDR667
-	   0x3D-->3.75ns Freq=266 DDR533
-	   0x50-->5.0ns Freq=200  DDR400
-	   0x60-->6.0ns Freq=166  DDR333
-	   0x75-->7.5ns Freq=133  DDR266
-	   0xA0-->10.0ns Freq=100 DDR200
+	   0x25-->2.5ns Freq = 400  DDR800
+	   0x30-->3.0ns Freq = 333  DDR667
+	   0x3D-->3.75ns Freq = 266 DDR533
+	   0x50-->5.0ns Freq = 200  DDR400
+	   0x60-->6.0ns Freq = 166  DDR333
+	   0x75-->7.5ns Freq = 133  DDR266
+	   0xA0-->10.0ns Freq = 100 DDR200
 	 */
 	if (CycTime <= 0x25) {
 		DramAttr->DramFreq = DIMMFREQ_800;
diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c
index 00c199971c..427979646c 100644
--- a/src/northbridge/via/vx800/lpc.c
+++ b/src/northbridge/via/vx800/lpc.c
@@ -87,7 +87,7 @@ static void pci_routing_fixup(struct device *dev)
 
 	/* Standard usb components */
 	printk(BIOS_INFO, "setting usb1-2\n");
-//      pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
+//	pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
 
 	/* sound hardware */
 	printk(BIOS_INFO, "setting hdac audio\n");
@@ -108,8 +108,8 @@ static void setup_pm(device_t dev)
 	/* set ACPI irq to 9 */
 	pci_write_config8(dev, 0x82, 0x49);
 
-	/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
-//      pci_write_config16(dev, 0x84, 0x30f2);
+	/* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */
+//	pci_write_config16(dev, 0x84, 0x30f2);
 	pci_write_config16(dev, 0x84, 0x609a);	// 0x609a??
 
 	/* SMI output level to low, 7.5us throttle clock */
@@ -234,7 +234,7 @@ static void vx800_sb_init(struct device *dev)
 	pci_write_config8(dev, 0x6C, enables);
 
 	// Map 4MB of FLASH into the address space
-//      pci_write_config8(dev, 0x41, 0x7f);
+//	pci_write_config8(dev, 0x41, 0x7f);
 
 	// Set bit 6 of 0x40, because Award does it (IO recovery time)
 	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
@@ -337,13 +337,13 @@ static void southbridge_init(struct device *dev)
 		fadt->pm2_cnt_len = 1;//to support cpu-c3
 	#2
 		ssdt? ->every CPU has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC )
-       #3    write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
-	       1  enable SLP# asserts in C3 state  PMIORx26<1> =1
-		2    enable CPUSTP# asserts in C3 state;  PMIORx26<2> =1
-		3  CLKRUN# is always asserted  PMIORx26<3> =0
-		4    Disable PCISTP# When CLKRUN# is asserted
+	#3    write 0x17 in to PMIO = VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec.
+		1  enable SLP# asserts in C3 state  PMIORx26<1> = 1
+		2  enable CPUSTP# asserts in C3 state;  PMIORx26<2> = 1
+		3  CLKRUN# is always asserted  PMIORx26<3> = 0
+		4  Disable PCISTP# When CLKRUN# is asserted
 		1: PCISTP# will not assert When CLKRUN# is asserted
-		PMIORx26<4> =1
+		PMIORx26<4> = 1
 		5  This bit controls whether the CPU voltage is lowered when in C3/S1 state.
 		VRDSLP will be active in either this bit set in C3 or LVL4 register read
 		PMIORx26<0> =0
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index 6cfb1b9eaf..bf5909316a 100644
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -141,7 +141,7 @@ void SetUMARam(void)
 	pci_write_config8(vga_dev, 0xb2, ByteVal);
 
 	//set M1 size
-	//ByteVal=pci_read_config8(MEMCTRL, 0xa3);
+	//ByteVal = pci_read_config8(MEMCTRL, 0xa3);
 	//ByteVal = 0x02;
 	//pci_write_config8(MEMCTRL, 0xa3, ByteVal);
 
@@ -216,7 +216,7 @@ void SetUMARam(void)
 	ByteVal = inb(0x03CC);
 	ByteVal |= 0x03;
 	outb(ByteVal, 0x03C2);
-	//  ByteVal=inb(0x03C2);
+	//  ByteVal = inb(0x03C2);
 	//   ByteVal |= 0x01;
 	//   outb(ByteVal,0x03C2);
 
@@ -318,7 +318,7 @@ void SetUMARam(void)
 	outb(0x22, 0x03c5);
 
 	//start : For enable snapshot mode control
-	// program 3C5 for SNAPSHOT Mode control, set RxF3h=1Ah
+	// program 3C5 for SNAPSHOT Mode control, set RxF3h = 1Ah
 	outb(0xf3, 0x03c4);
 	ByteVal = inb(0x03c5);
 	ByteVal = (ByteVal & 0xE5) | 0x1A;
@@ -393,7 +393,7 @@ void SetUMARam(void)
 		0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 	};
 
-	//for (i=0;i<0xc0;i++)
+	//for (i = 0;i < 0xc0;i++)
 	for (i = 0; i < 0x40; i++)
 	{
 		outb(table3c0space[i], 0x03c0 + i);
diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c
index 61d4563dab..664e91583a 100644
--- a/src/northbridge/via/vx800/vga.c
+++ b/src/northbridge/via/vx800/vga.c
@@ -48,13 +48,13 @@
 
 static int via_vx800_int15_handler(void)
 {
-	int res=0;
+	int res = 0;
 	printk(BIOS_DEBUG, "via_vx800_int15_handler\n");
 	switch(X86_EAX & 0xffff) {
 	case 0x5f19:
-		X86_EAX=0x5f;
-		X86_ECX=0x03;
-		res=1;
+		X86_EAX = 0x5f;
+		X86_ECX = 0x03;
+		res = 1;
 		break;
 	case 0x5f18:
 	{
@@ -104,11 +104,11 @@ static int via_vx800_int15_handler(void)
 		res = 1;
 		break;
 	case 0x5f02:
-		X86_EAX=0x5f;
-		X86_EBX= (X86_EBX & 0xffff0000) | 2;
-		X86_ECX= (X86_ECX & 0xffff0000) | 0x401;  // PAL + crt only
-		X86_EDX= (X86_EDX & 0xffff0000) | 0;  // TV Layout - default
-		res=1;
+		X86_EAX = 0x5f;
+		X86_EBX = (X86_EBX & 0xffff0000) | 2;
+		X86_ECX = (X86_ECX & 0xffff0000) | 0x401;  // PAL + crt only
+		X86_EDX = (X86_EDX & 0xffff0000) | 0;  // TV Layout - default
+		res = 1;
 		break;
 	case 0x5f0f:
 		X86_EAX = 0x005f;