northbridge/via: Add space around operators

Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16623
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

4 files changed, 11 insertions, 11 deletions

diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c
index 6109ea02c0..44aa743f88 100644
--- a/src/northbridge/via/cx700/early_smbus.c
+++ b/src/northbridge/via/cx700/early_smbus.c
@@ -142,7 +142,7 @@ static void set_ics_data(unsigned char dev, int data, char len)
 		outb(0xff, SMBBLKDAT);
 	}
 
-	//for (i=0; i < len; i++)
+	//for (i = 0; i < len; i++)
 	//      outb(data[i],SMBBLKDAT);
 
 	outb(dev, SMBXMITADD);
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index 2d7431628f..e9e4d98e33 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -87,7 +87,7 @@ static void setup_pm(device_t dev)
 	/* set ACPI irq to 9 */
 	pci_write_config8(dev, 0x82, 0x49);
 
-	/* Primary interupt channel, define wake events 0=IRQ0 15=IRQ15 1=en. */
+	/* Primary interupt channel, define wake events 0 = IRQ0 15 = IRQ15 1 = en. */
 	pci_write_config16(dev, 0x84, 0x609a);
 
 	/* SMI output level to low, 7.5us throttle clock */
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index 7d3fcbeb0b..14a17d4771 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -90,7 +90,7 @@
 
 #define REGISTERPRESET(bus,dev,fun,bdfspec) \
 	{ u8 j, reg; \
-		for (j=0; j<(sizeof((bdfspec))/sizeof(struct regmask)); j++) { \
+		for (j = 0; j < (sizeof((bdfspec))/sizeof(struct regmask)); j++) { \
 			printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \
 			printk(BIOS_DEBUG, "%02x", (bdfspec)[j].reg); \
 			printk(BIOS_DEBUG, "\n"); \
@@ -303,8 +303,8 @@ static const u8 Init_Rank_Reg_Table[] = {
 
 static const u16 DDR2_MRS_table[] = {
 /* CL:	2,     3,     4,     5 */
-	0x150, 0x1d0, 0x250, 0x2d0,	/* BL=4 ;Use 1X-bandwidth MA table to init DRAM */
-	0x158, 0x1d8, 0x258, 0x2d8,	/* BL=8 ;Use 1X-bandwidth MA table to init DRAM */
+	0x150, 0x1d0, 0x250, 0x2d0,	/* BL = 4 ;Use 1X-bandwidth MA table to init DRAM */
+	0x158, 0x1d8, 0x258, 0x2d8,	/* BL = 8 ;Use 1X-bandwidth MA table to init DRAM */
 };
 
 #define	MRS_DDR2_TWR2	((0 << 15) | (0 << 20) | (1 << 12))
@@ -1050,7 +1050,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 	/* Step 17. Mode register set. Wait 200us. */
 	printk(BIOS_SPEW, "\nRAM Enable 4: Mode register set\n");
 
-	//safe value for now, BL=8, WR=4, CAS=4
+	//safe value for now, BL = 8, WR = 4, CAS = 4
 	do_ram_command(ctrl, RAM_COMMAND_MRS);
 	udelay(200);
 
diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c
index 16f0ea0061..7cb84d2d7e 100644
--- a/src/northbridge/via/cx700/vga.c
+++ b/src/northbridge/via/cx700/vga.c
@@ -42,7 +42,7 @@
 
 static int via_cx700_int15_handler(void)
 {
-	int res=0;
+	int res = 0;
 	u8 mem_speed;
 
 #define MEMORY_SPEED_66MHZ	(0 << 4)
@@ -83,7 +83,7 @@ static int via_cx700_int15_handler(void)
 		X86_ECX = 0x00000000; // 0 -> default
 		// TV Layout - default
 		X86_EDX = (X86_EDX & 0xffffff00) | 0;
-		res=1;
+		res = 1;
 		break;
 
 	case 0x5f0b:	/* Get Expansion Setting */
@@ -91,12 +91,12 @@ static int via_cx700_int15_handler(void)
 
 		X86_ECX = X86_ECX & 0xffffff00; // non-expansion
 		// regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion
-		res=1;
+		res = 1;
 		break;
 
 	case 0x5f0f:	/* VGA Post Completion */
 		X86_EAX = (X86_EAX & 0xffff0000 ) | 0x5f;
-		res=1;
+		res = 1;
 		break;
 
 	case 0x5f18:
@@ -113,7 +113,7 @@ static int via_cx700_int15_handler(void)
 
 		X86_EBX |= memory_mapping[mem_speed];
 
-		res=1;
+		res = 1;
 		break;
 
 	default: