via/cx700: Use zeroptr over 0

This eliminates all "ud2" instances from romstage disassembly.

Change-Id: I3b0c8322a4ca4a851b0cce8f3941425d9cb30383
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/13488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 42 insertions, 42 deletions

diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index 249f265376..2016a87e2f 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -989,7 +989,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 
 	// Step 4
 	printk(BIOS_SPEW, "SEND: ");
-	read32((void *)0);
+	read32(zeroptr);
 	printk(BIOS_SPEW, "OK\n");
 
 	// Step 5
@@ -1001,7 +1001,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 
 	// Step 7
 	printk(BIOS_SPEW, "SEND: ");
-	read32((void *)0);
+	read32(zeroptr);
 	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 8. Mode register set. */
@@ -1029,7 +1029,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 
 	// Step 12
 	printk(BIOS_SPEW, "SEND: ");
-	read32((u32 *)0x0);
+	read32(zeroptr);
 	printk(BIOS_SPEW, "OK\n");
 
 	/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
@@ -1040,7 +1040,7 @@ static void step_2_19(const struct mem_controller *ctrl)
 	// Step 16: Repeat Step 14 and 15 another 7 times
 	for (i = 0; i < 8; i++) {
 		// Step 14
-		read32((u32 *)0);
+		read32(zeroptr);
 		printk(BIOS_SPEW, ".");
 
 		// Step 15
@@ -1127,45 +1127,45 @@ static void sdram_calc_size(const struct mem_controller *ctrl, u8 num)
 	u8 ca, ra, ba, reg;
 	ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS);
 	if (ba == 8) {
-		write8((void *)0, 0x0d);
-		ra = read8((void *)0);
+		write8(zeroptr, 0x0d);
+		ra = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_RA_12_8bk), 0x0c);
-		ra = read8((void *)0);
+		ra = read8(zeroptr);
 
-		write8((void *)0, 0x0a);
-		ca = read8((void *)0);
+		write8(zeroptr, 0x0a);
+		ca = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_CA_09_8bk), 0x0c);
-		ca = read8((void *)0);
+		ca = read8(zeroptr);
 
-		write8((void *)0, 0x03);
-		ba = read8((void *)0);
+		write8(zeroptr, 0x03);
+		ba = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
-		ba = read8((void *)0);
+		ba = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
-		ba = read8((void *)0);
+		ba = read8(zeroptr);
 	} else {
-		write8((void *)0, 0x0f);
-		ra = read8((void *)0);
+		write8(zeroptr, 0x0f);
+		ra = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_RA_14), 0x0e);
-		ra = read8((void *)0);
+		ra = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_RA_13), 0x0d);
-		ra = read8((void *)0);
+		ra = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_RA_12), 0x0c);
-		ra = read8((void *)0);
+		ra = read8(zeroptr);
 
-		write8((void *)0, 0x0c);
-		ca = read8((void *)0);
+		write8(zeroptr, 0x0c);
+		ca = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_CA_12), 0x0b);
-		ca = read8((void *)0);
+		ca = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_CA_11), 0x0a);
-		ca = read8((void *)0);
+		ca = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_CA_09), 0x09);
-		ca = read8((void *)0);
+		ca = read8(zeroptr);
 
-		write8((void *)0, 0x02);
-		ba = read8((void *)0);
+		write8(zeroptr, 0x02);
+		ba = read8(zeroptr);
 		write8((void *)(1 << SDRAM1X_BA1), 0x01);
-		ba = read8((void *)0);
+		ba = read8(zeroptr);
 	}
 
 	if (ra < 10 || ra > 15)
@@ -1271,17 +1271,17 @@ static void sdram_enable(const struct mem_controller *ctrl)
 			if (reg8) {
 				sdram_set_vr(ctrl, i);
 				sdram_ending_addr(ctrl, i);
-				write32((void *)0, 0x55555555);
+				write32(zeroptr, 0x55555555);
 				write32((void *)4, 0x55555555);
 				udelay(15);
-				if (read32((void *)0) != 0x55555555)
+				if (read32(zeroptr) != 0x55555555)
 					break;
 				if (read32((void *)4) != 0x55555555)
 					break;
-				write32((void *)0, 0xaaaaaaaa);
+				write32(zeroptr, 0xaaaaaaaa);
 				write32((void *)4, 0xaaaaaaaa);
 				udelay(15);
-				if (read32((void *)0) != 0xaaaaaaaa)
+				if (read32(zeroptr) != 0xaaaaaaaa)
 					break;
 				if (read32((void *)4) != 0xaaaaaaaa)
 					break;
@@ -1304,17 +1304,17 @@ static void sdram_enable(const struct mem_controller *ctrl)
 				sdram_set_vr(ctrl, i);
 				sdram_ending_addr(ctrl, i);
 
-				write32((void *)0, 0x55555555);
+				write32(zeroptr, 0x55555555);
 				write32((void *)4, 0x55555555);
 				udelay(15);
-				if (read32((void *)0) != 0x55555555)
+				if (read32(zeroptr) != 0x55555555)
 					break;
 				if (read32((void *)4) != 0x55555555)
 					break;
-				write32((void *)0, 0xaaaaaaaa);
+				write32(zeroptr, 0xaaaaaaaa);
 				write32((void *)4, 0xaaaaaaaa);
 				udelay(15);
-				if (read32((void *)0) != 0xaaaaaaaa)
+				if (read32(zeroptr) != 0xaaaaaaaa)
 					break;
 				if (read32((void *)4) != 0xaaaaaaaa)
 					break;
@@ -1358,17 +1358,17 @@ static void sdram_enable(const struct mem_controller *ctrl)
 			sdram_set_vr(ctrl, i);
 			sdram_ending_addr(ctrl, i);
 			if (reg8 == 4) {
-				write8((void *)0, 0x02);
-				val = read8((void *)0);
+				write8(zeroptr, 0x02);
+				val = read8(zeroptr);
 				write8((void *)(1 << SDRAM1X_BA1), 0x01);
-				val = read8((void *)0);
+				val = read8(zeroptr);
 			} else {
-				write8((void *)0, 0x03);
-				val = read8((void *)0);
+				write8(zeroptr, 0x03);
+				val = read8(zeroptr);
 				write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
-				val = read8((void *)0);
+				val = read8(zeroptr);
 				write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
-				val = read8((void *)0);
+				val = read8(zeroptr);
 			}
 			if (val < dl)
 				dl = val;