diff options
author | Corey Osgood <corey.osgood@gmail.com> | 2008-02-21 00:56:14 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2008-02-21 00:56:14 +0000 |
commit | bd3f93e33038be965c971a6974d580f55934b854 (patch) | |
tree | 52287af10f52f09c81e19ce64c95b8a9973474df /src/northbridge/via/cn700/cn700.h | |
parent | f327d9f9540971518e1661e1f50d30ffa6b74173 (diff) |
Add support for the Via CN700 with a C7 CPU and DDR2 RAM. Only a single DIMM is
working for now, and more work is needed for it to be fully dynamic. However,
just about any 128MB-512MB DIMM should work.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/via/cn700/cn700.h')
-rw-r--r-- | src/northbridge/via/cn700/cn700.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/northbridge/via/cn700/cn700.h b/src/northbridge/via/cn700/cn700.h new file mode 100644 index 0000000000..b9d7ad3455 --- /dev/null +++ b/src/northbridge/via/cn700/cn700.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ROMCC__ +static void cn700_noop(){} +#endif + +/* VGA stuff */ +#define SR_INDEX 0x3c4 +#define SR_DATA 0x3c5 +#define CRTM_INDEX 0x3b4 +#define CRTM_DATA 0x3b5 +#define CRTC_INDEX 0x3d4 +#define CRTC_DATA 0x3d5 + +/* Memory Controller Registers */ +#define RANK0_END 0x40 +#define RANK1_END 0x41 +#define RANK2_END 0x42 +#define RANK3_END 0x43 +#define RANK0_START 0x48 +#define RANK1_START 0x49 +#define RANK2_START 0x4a +#define RANK3_START 0x4b +#define DDR_PAGE_CTL 0x69 +#define DRAM_REFRESH_COUNTER 0x6a +#define DRAM_MISC_CTL 0x6b +#define CH_A_DQS_OUTPUT_DELAY 0x70 +#define CH_A_MD_OUTPUT_DELAY 0x71 + +/* RAM Init Commands */ +#define RAM_COMMAND_NORMAL 0x0 +#define RAM_COMMAND_NOP 0x1 +#define RAM_COMMAND_PRECHARGE 0x2 +#define RAM_COMMAND_MRS 0x3 +#define RAM_COMMAND_CBR 0x4 |