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author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-06-25 18:37:45 -0500 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-11-15 02:44:10 +0100 |
commit | 11739a48ce08d1ef11bfd54670ec23a1ee6daccd (patch) | |
tree | c76c1e0ae5fe05e8fbe4ef30dc41cedeeeb2121a /src/northbridge/rdc/r8610 | |
parent | 9426e4fcf5f49c46fa1e5cbe9fc38d2575cfdb62 (diff) |
northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
AMD Opteron processors contain a very fragile phy phase detection circuit.
Additionally, the algorithm given in the BKDG does not function as intended;
this was verified both on real hardware via execution trace and on paper
with values read back from multiple CPUs and DIMMs.
As a result, the phy training algorithm given in the BKDG has been
replaced with a phy training algorithm developed at Raptor Engineering.
This particular patch is the first part of that algorithm; the code
is updated in future patches but this should exist in the historical
record in case something breaks down in the later sections of code.
Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12007
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/rdc/r8610')
0 files changed, 0 insertions, 0 deletions