diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-25 11:40:00 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-18 21:03:05 +0100 |
| commit | e39a8a9c092ed66686632d591ec84ed7a6165a50 (patch) | |
| tree | 498408ef8c9d41fd4adc3bd3cf1361f8a1c3f3e3 /src/northbridge/intel | |
| parent | bfca67078cfddc18994fa6bbe9094a2ecca275a3 (diff) | |
intel/sandybridge: Use romstage_handoff for S3
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I5b218ce3046493b92952e47610c41b07efa4d1de
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17455
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 21 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 21 |
2 files changed, 8 insertions, 34 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 86d1c002a5..ef97a1af84 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -23,6 +23,7 @@ #include <elog.h> #include <cbmem.h> #include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> #include "sandybridge.h" static void sandybridge_setup_bars(void) @@ -226,19 +227,13 @@ void sandybridge_early_initialization(int chipset_type) void northbridge_romstage_finalize(int s3resume) { - MCHBAR16(SSKPD) = 0xCAFE; - -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ + struct romstage_handoff *handoff; - if (s3resume) { + MCHBAR16(SSKPD) = 0xCAFE; - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); } diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index a67b84ddf4..fe1a07c570 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -470,26 +470,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type=0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type=3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type=0; - break; - } -#endif -} - static u32 northbridge_get_base_reg(device_t dev, int reg) { u32 value; @@ -521,7 +501,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .scan_bus = 0, .ops_pci = &intel_pci_ops, .acpi_fill_ssdt_generator = generate_cpu_entries, |