diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-02 19:01:24 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-08 05:26:49 +0000 |
| commit | d04957970cc55743db3d896b3975570b42f05d95 (patch) | |
| tree | ee365072981388d4812b9c3bbcf77b32f552f1c5 /src/northbridge/intel | |
| parent | f8d47455f7826913dc8d19663d04c8a5c4c36ba2 (diff) | |
nb/intel/haswell: Drop `gpu_panel_port_select`
The corresponding bits in PP_ON_DELAYS are reserved MBZ.
Change-Id: Icd2554c928a5908dfb354b81d3e6c5b5f242f1d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/chip.h | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 28c082838d..73375d788d 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -17,7 +17,6 @@ struct northbridge_intel_haswell_config { u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ - u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */ diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index c466c09d86..5a6bb8e1de 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -304,7 +304,6 @@ static void gma_setup_panel(struct device *dev) /* Setup Panel Power On Delays */ reg32 = gtt_read(PCH_PP_ON_DELAYS); if (!reg32) { - reg32 = (conf->gpu_panel_port_select & 0x3) << 30; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); gtt_write(PCH_PP_ON_DELAYS, reg32); |