diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2021-01-31 08:26:01 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 08:59:10 +0000 |
| commit | c4d1b47ad95f479981de9a30b5906c81dd720377 (patch) | |
| tree | 75a135ad2297ae222fba1ffefeaa9021ad876eff /src/northbridge/intel | |
| parent | b96c3587517448498412ac7b31bf9af405a3c518 (diff) | |
nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>
Also rename 'reg' to 'reg32'.
Change-Id: Id741f636162a8a228bca069637993422deb5e09c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/gm45/bootblock.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index 9c45f7e3f8..e2cabdb166 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <arch/pci_io_cfg.h> #include <assert.h> -#include <device/pci_ops.h> #include <types.h> #include "gm45.h" @@ -31,7 +31,7 @@ void bootblock_early_northbridge_init(void) * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. */ - const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0); - pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg); + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); } |