diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-12 15:00:03 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-05-14 07:30:20 +0200 |
| commit | a6130fc8f9c00e0c545389b4e407f0b745435a56 (patch) | |
| tree | e6256608d70f2765c046c706c821d3db80fe5bdb /src/northbridge/intel | |
| parent | a823f9b545b4a172c1c0f778b773f9ca13f0791e (diff) | |
intel: Drop obsolete comments on MTRR usage
Problem with UMA region allocation was fixed when MTRRs changed to use
memrange implementation.
Change-Id: I420dac30de2836a91596d81f88bb45b46f248532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5719
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/northbridge.c | 11 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/northbridge.c | 11 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 11 |
3 files changed, 0 insertions, 33 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index d5b1575d23..2922ca0e6a 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -102,17 +102,6 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size; - /* Using uma_resource() here would fail as base & size cannot - * be used as-is for a single MTRR. This would cause excessive - * use of MTRRs. - * - * Use of mmio_resource() instead does not create UC holes by using - * MTRRs, but making these regions uncacheable is taken care of by - * making sure they do not overlap with any ram_resource(). - * - * The resources can be changed to use separate mmio_resource() - * calls after MTRR code is able to merge them wisely. - */ mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index d94bc09ba8..639d24568b 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -134,17 +134,6 @@ static void mc_read_resources(device_t dev) ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768)); - /* Using uma_resource() here would fail as base & size cannot - * be used as-is for a single MTRR. This would cause excessive - * use of MTRRs. - * - * Use of mmio_resource() instead does not create UC holes by using - * MTRRs, but making these regions uncacheable is taken care of by - * making sure they do not overlap with any ram_resource(). - * - * The resources can be changed to use separate mmio_resource() - * calls after MTRR code is able to merge them wisely. - */ mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5440140089..1fd252bcc0 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -100,17 +100,6 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size; - /* Using uma_resource() here would fail as base & size cannot - * be used as-is for a single MTRR. This would cause excessive - * use of MTRRs. - * - * Use of mmio_resource() instead does not create UC holes by using - * MTRRs, but making these regions uncacheable is taken care of by - * making sure they do not overlap with any ram_resource(). - * - * The resources can be changed to use separate mmio_resource() - * calls after MTRR code is able to merge them wisely. - */ mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { |