diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-15 22:10:13 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-22 07:25:37 +0000 |
| commit | a3868296ceee36a0562631978d3d522c19896322 (patch) | |
| tree | 5bb17fe852ce89d8c670d37af80c0911fbb4b98e /src/northbridge/intel | |
| parent | e9fa37894e59a35deeb897dcb323765d53603754 (diff) | |
nb/intel/ironlake: Do not call `collect_system_info` twice
Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.
Tested on out-of-tree HP 630, still boots.
Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 22 |
1 files changed, 7 insertions, 15 deletions
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 407be5585e..3908504832 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1470,16 +1470,6 @@ static void collect_system_info(struct raminfo *info) int i; unsigned int channel; - /* Wait for some bit, maybe TXT clear. */ - while (!(read8((u8 *)0xfed40000) & (1 << 7))) - ; - - if (!info->memory_reserved_for_heci_mb) { - /* Wait for ME to be ready */ - intel_early_me_init(); - info->memory_reserved_for_heci_mb = intel_early_me_uma_size(); - } - for (i = 0; i < 3; i++) { capid0[i] = pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2)); printk(BIOS_DEBUG, "CAPID0[%d] = 0x%08x\n", i, capid0[i]); @@ -3713,16 +3703,18 @@ void raminit(const int s3resume, const u8 *spd_addrmap) info.training.reg_178 = 0; info.training.reg_10b = 0; - info.memory_reserved_for_heci_mb = 0; + /* Wait for some bit, maybe TXT clear. */ + while (!(read8((u8 *)0xfed40000) & (1 << 7))) + ; + + /* Wait for ME to be ready */ + intel_early_me_init(); + info.memory_reserved_for_heci_mb = intel_early_me_uma_size(); /* before SPD */ timestamp_add_now(101); if (!s3resume || 1) { // possible error - pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); // = 0x80 - - collect_system_info(&info); - memset(&info.populated_ranks, 0, sizeof(info.populated_ranks)); info.use_ecc = 1; |