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authorArthur Heymans <arthur@aheymans.xyz>2023-07-05 10:57:30 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2023-07-12 08:36:59 +0000
commit9a7198392a2d98cdc7ba3d6d454de29751afb25f (patch)
tree0d4a4fbdc3781f81f9afa7f1f0fbee905afb6c52 /src/northbridge/intel
parent6665c296e3d2441090692dc0027d2bb5709c1245 (diff)
nb/e7505: Rework nb resource reading
- Use newer functions and avoid the * / KiB dance - Use existing functions for figuring out TSEG and UMA - Don't have resources overlap Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Ia8562660cf69d188b0cab4869aa3190f014dbfdc Reviewed-on: https://review.coreboot.org/c/coreboot/+/76276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/e7505/northbridge.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index a353759d3b..b51b2ab5c4 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -6,13 +6,13 @@
#include <device/device.h>
#include <device/pci.h>
#include <cpu/cpu.h>
+#include <cpu/x86/smm.h>
#include "e7505.h"
static void mch_domain_read_resources(struct device *dev)
{
int idx;
- unsigned long tolmk;
uint64_t tom, remapbase, remaplimit;
struct device *mc_dev;
@@ -22,9 +22,6 @@ static void mch_domain_read_resources(struct device *dev)
if (!mc_dev)
die("Could not find MCH device\n");
- tolmk = pci_read_config16(mc_dev, TOLM) >> 11;
- tolmk <<= 17;
-
tom = pci_read_config8(mc_dev, DRB_ROW_7);
tom <<= 26;
@@ -39,12 +36,15 @@ static void mch_domain_read_resources(struct device *dev)
/* Report the memory regions */
idx = 10;
- ram_resource_kb(dev, idx++, 0, tolmk);
- mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
-
- uintptr_t tseg_memory_base = northbridge_get_tseg_base();
- size_t tseg_memory_size = northbridge_get_tseg_size();
- mmio_resource_kb(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB);
+ ram_range(dev, idx++, 0, 0xa0000);
+ mmio_from_to(dev, idx++, 0xa0000, 0xc0000);
+ ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
+
+ uintptr_t tseg_base;
+ size_t tseg_size;
+ smm_region(&tseg_base, &tseg_size);
+ ram_from_to(dev, idx++, 1 * MiB, tseg_base);
+ mmio_range(dev, idx++, tseg_base, tseg_size);
ASSERT(tom == remapbase);
upper_ram_end(dev, idx++, remaplimit);