summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
diff options
context:
space:
mode:
authorSven Schnelle <svens@stackframe.org>2012-01-10 12:16:38 +0100
committerPatrick Georgi <patrick@georgi-clan.de>2012-01-10 12:54:09 +0100
commit784ffb3db694dd2c964d9a4e1c6657a835b2d141 (patch)
tree7998d307db61ef6518473518b5a71193153787d1 /src/northbridge/intel
parent8fa2787a0d74c70ca9497abf1483ab9dd223e642 (diff)
i945: fix tsc udelay()
The comparision is the wrong way round: as long as tsc is below tsc1, the timeout is not reached Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/530 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/i945/udelay.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 6b3882bc18..9170335bd5 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -78,7 +78,7 @@ void udelay(u32 us)
do {
tsc = rdtsc();
- } while ((tsc.hi > tsc1.hi)
- || ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo)));
+ } while ((tsc.hi < tsc1.hi)
+ || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
}