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authorNico Huber <nico.h@gmx.de>2019-11-17 02:58:00 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-18 11:52:24 +0000
commit47bf4986815407393c1cf02922c882ed0f336bb2 (patch)
tree210fdf4d4a0bafdc5aed1356a40f1f42c6293df9 /src/northbridge/intel
parent6760e0bdcd37e904c121800652cd2ac3920d9cd9 (diff)
nb/intel/sandybridge/mrc: Handle P2P disabling via devicetree
Some Sandy Bridge boards disabled the PCI-to-PCI bridge early to avoid probing by the MRC. We can do that for all boards instead, based on the devicetree setting. Change-Id: Ie64774628fde77db2a379bdba6a921a31e52fa0d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index a8acfbf980..29c766a59f 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -18,6 +18,7 @@
#include <bootmode.h>
#include <cf9_reset.h>
#include <string.h>
+#include <device/device.h>
#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cbmem.h>
@@ -382,6 +383,16 @@ static void devicetree_fill_pei_data(struct pei_data *pei_data)
pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams;
}
+static void disable_p2p(void)
+{
+ /* Disable PCI-to-PCI bridge early to prevent probing by MRC. */
+ const struct device *const p2p = pcidev_on_root(0x1e, 0);
+ if (p2p && p2p->enabled)
+ return;
+
+ RCBA32(FD) |= PCH_DISABLE_P2P;
+}
+
void perform_raminit(int s3resume)
{
int cbmem_was_initted;
@@ -423,6 +434,8 @@ void perform_raminit(int s3resume)
}
}
+ disable_p2p();
+
pei_data.boot_mode = s3resume ? 2 : 0;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);